Voltage multiplier employing clock gated transistor chain

Details Voltage multiplier employing clock gated transistor chain Voltage multiplier employing clock gated transistor chain

1978-03-22

1980-07-22

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307221C, 328160, G11C 1140, H03K 702

Patent

active

042141745

ABSTRACT:
A voltage multiplier circuit arrangement comprises a plurality of transistors connected a series between an input and an output of said arrangement, and first and second input lines arranged to have differential alternating voltage applied between them. Successive junctions between adjacent transistors are connected via respective capacitors to alternate ones of the first and second input lines. The control electrode (e.g. the gate or base electrode) of each one of said transistors is connected to a junction of two adjacent transistors, the latter being nearer to the output of said arrangement than is the one transistor. The junction is connected via one of the capacitors with the input line with which said one transistor is connected.

REFERENCES:
patent: 3666972 (1972-05-01), Sanster
patent: 3912944 (1975-10-01), Mulder et al.
patent: 3939364 (1976-02-01), Adam et al.

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