Voltage multiplier compatible with a self-isolated C/DMOS proces

Details Voltage multiplier compatible with a self-isolated C/DMOS proces Voltage multiplier compatible with a self-isolated C/DMOS proces

1988-05-02

1989-12-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307579, 3072968, 307529, 307501, 307304, H03K 17687, H03K 326

Patent

active

048885053

ABSTRACT:
A CMOS structure is employed to create an isolated large area power output transistor along with a voltage multiplier that acts to develop an overdrive bias in response to clock pulses. The circuit can be employed to couple a relatively low power supply voltage to an output terminal while encountering a small voltage drop across the power transistor.

REFERENCES:
patent: Re32526 (1987-10-01), Hochstein
patent: 3824447 (1974-07-01), Kuwabara
patent: 4599555 (1986-07-01), Damiano et al.
patent: 4603269 (1986-07-01), Hochstein
patent: 4616303 (1986-10-01), Mauthe
patent: 4649289 (1987-03-01), Nakano

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