Voltage multiplier circuit with reduced back-gate bias effect

Details Voltage multiplier circuit with reduced back-gate bias effect Voltage multiplier circuit with reduced back-gate bias effect

1988-11-07

1990-05-01

Wong, Peter S.

Electric power conversion systems

Current conversion

With voltage multiplication means

363147, 357 41, H02M 725

Patent

active

049224034

ABSTRACT:
A voltage multiplier includes a series connection of rectifier elements which are alternately rendered conductive by alternately applying complementary clock signals to capacitances which are connected to junction points of pairs of neighboring rectifier elements. The rectifier element is constructed by means of field effect transistors so that the well in the substrate in which the rectifier element is formed receives either the anode voltage or the cathode voltage. This prevents the occurrence of the so-called back-gate bias effect which increases the threshold voltage of the rectifier element and limits the output voltage of the voltage multipler.

REFERENCES:
patent: 4061929 (1977-12-01), Asano
patent: 4481566 (1984-11-01), Hoffman et al.
patent: 4559548 (1985-12-01), Iizuka et al.
patent: 4621315 (1986-11-01), Vaughn et al.
Carr et al., "MOS/LSI Design and Application", McGraw-Hill, 1972, pp. 56-57.

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