Voltage monitoring circuit capable of reducing power dissipation

Details Voltage monitoring circuit capable of reducing power dissipation Voltage monitoring circuit capable of reducing power dissipation

1997-03-21

1999-07-27

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327 77, 327312, H03K 3037, H03K 522

Patent

active

059296798

ABSTRACT:
In a buffering circuit, a CMOS inverter is connected between a node and a ground terminal. A source-follower-type MOS transistor is connected between a power supply terminal and the node, and a approximately definite voltage is applied to a gate of the source-follower-type MOS transistor. A MOS transistor is connected in parallel to the source-follower-type MOS transistor, and an inverted signal of an output signal of the CMOS inverter is applied to a gate of the MOS transistor.

REFERENCES:
patent: 4506168 (1985-03-01), Uya
patent: 4563594 (1986-01-01), Koyama
patent: 4859873 (1989-03-01), O'Shaughnessy et al.

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