Voltage margining circuit for flash eprom

Details Voltage margining circuit for flash eprom Voltage margining circuit for flash eprom

1988-01-12

1989-10-17

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365148, 365218, 365177, 307 28, 307 29, G11C 1134, G11C 1100, G11C 700, H02J 110

Patent

active

048751880

ABSTRACT:
A circuit is described for providing internal voltage margining for a flash EPROM to verify erasing and programming. Matched transistors are used to develop the internal margined voltage so as to provide a potential which is substantially independent of process variations. Different potentials are used to verify programming and erasing.

REFERENCES:
patent: 4460982 (1984-07-01), Gee et al.
patent: 4503524 (1985-03-01), McElroy
patent: 4694430 (1987-09-01), Rosier
patent: 4720816 (1988-01-01), Matsuoka et al.
"A 256-K Bit Flash E.sup.2 Prom Using Triple-Polysilicon Technology", IEEE Journal Solid-State Circuits, vol. SC-22, No. 4, Aug. 1987, (pp. 548-552).

Affiliated with

Also associated with

Rating

Voltage margining circuit for flash eprom does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage margining circuit for flash eprom, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage margining circuit for flash eprom will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1747598