Amplifiers – With periodic switching input-output
Reexamination Certificate
2001-09-28
2003-11-25
Shingleton, Michael B (Department: 2817)
Amplifiers
With periodic switching input-output
C703S001000, C703S013000, C341S120000, C330S258000, C330S252000, C330S259000
Reexamination Certificate
active
06653893
ABSTRACT:
BACKGROUND
This invention is in general related to input/output (i.e., I/O) data communication circuits and more particularly to testing the voltage margin of a communication link at a receiver circuit.
I/O circuits act as the interface between different logic functional units of an electrical system. The functional units may be implemented in separate integrated circuit dies (i.e., IC chips) of the system. These chips may be in separate IC packages that have been soldered to a printed wiring board (i.e., PWB). The chips communicate with each other over one or more conductive transmission lines. The transmission lines may be a parallel bus formed on a PWB, and they may be of the point-to-point or multi-drop variety. Alternatively, the transmission line may be a serial link such as a coaxial cable. In both cases, each chip has an I/O circuit that includes a driver and a receiver for transmitting and detecting symbols. The driver and receiver translate between on-chip signaling and signaling that is suitable for high speed transmission (e.g., at several hundred megabits per second and higher) over a transmission line. In a ‘bidirectional link’, the driver and receiver pair are connected to the same transmission line.
In multi-level data communications, each transmitted symbol can have one of three or more values. For example, each symbol in a four pulse amplitude modulation (i.e., 4 PAM) link may only be a 0, 1, 2, or 3. In contrast, each symbol in a binary communication link may only be 0 or 1. For the binary link, the two symbol values may be detected using a single comparator whose reference level is fixed at the midpoint between the 0 and 1 nominal signal levels. A single digital ‘bit’ at the output of the comparator yields the symbol value. In contrast, a 4 PAM multi-level receiver may use three comparators whose respective reference levels have been fixed with respect to the four nominal signal levels, such that four different signal levels can be discerned. A three-bit number that appears at the output of the comparators identifies any one of four detected symbol values.
The voltage margin is a figure of merit for a communication link, and is typically associated with the receiver circuit. Voltage margin may be defined as the maximum excess (or reduction) beyond a nominal, received signal level, that still results in the receiver detecting the correct symbol value (which is ordinarily represented by the nominal level). For instance, consider a 4 PAM link in which a signal level of +3.0 Volts represents the nominal signal level for symbol #
3
, a signal level of +1.0 Volt represents the nominal level for symbol #
2
, and a signal level of −1.0 Volt represents symbol #
1
. If the comparator reference levels used to discern between symbol #
2
and the other symbols is selected to be +2.0 Volts and 0.0 Volts, then the maximum excess above 1.0 Volt that would still permit the comparator to correctly detect symbol #
2
would be approximately one (1) Volt. In addition, the maximum reduction below 1.0 Volt that would still permit the comparator to correctly detect symbol #
2
would also be one (1) Volt. Thus, the voltage margin for symbol #
2
, at this particular receiver circuit, would be one (1) Volt.
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Peralías et al. “A PFT Technique for Analog-to-Digital Converters with Digital Correction” VLSI Test Symposium, 15thIEEE Apr. 27-May 1, 1997 pp 302-307.
Casper Bryan K.
Haycock Matthew B.
Mooney Stephen R.
Blakely , Sokoloff, Taylor & Zafman LLP
Shingleton Michael B
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