Amplifiers – With semiconductor amplifying device – Including plural stages cascaded
Reexamination Certificate
2000-04-06
2002-01-29
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including plural stages cascaded
Reexamination Certificate
active
06342816
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to stabilizing the operational performance of MOS circuits and specifically to minimizing limitations on cascode amplifier circuit performance and reliability caused by excessive substrate current induced by hot electrons from high drain-to-source voltages.
BACKGROUND
In MOS amplifier and current mirror circuits, transistors biased into the saturation to region can experience an undesirable substrate current arising from impact ionization (due to the so-called “hot electron” effect). Impact ionization in the MOSFET channel is described in the literature and is generally known by circuit design practitioners.
A physical model of this effect is depicted in a single p-well n-channel transistor
300
of FIG.
3
. Transistor
300
is shown biased in saturation, that is, with the inversion layer
302
under the gate oxide
304
terminating short of the edge of the actual drain diffusion
306
at a pinch-off point
308
. This pinch-off point
308
occurs at a drain-to-source voltage (Vds) of Vdssat. The drain current ID increases relatively little as drain-to-source voltage Vds increases beyond Vdssat. The location of the pinch-off point
308
is shown as offset from actual edge of the diffusion
306
, which is the case when Vds is greater than Vdssat.
At constant gate-to-source voltage Vgs, the pinch-off point
308
moves relatively little as Vds increases. Consequently, the drain current ID changes relatively little as well. This is shown in the V-I characteristics of
FIG. 5
, where the ID vs. Vds operating characteristic shows the transistor operating in one of two regions, the triode region with low drain-source impedance, and the saturation region with high drain-source impedance.
Beyond Vdssat, the transistor region between the inversion layer end
308
and the edge of the drain
306
sustains nearly all of the increased voltage potential between drain and source. At sufficiently high Vds, the electric field in the depletion region between inversion layer
302
and the edge of drain
306
can cause electrons flowing from the end of the inversion layer
308
to the drain
306
(i.e., in the depletion region) to gain additional energy. With sufficient additional energy, the free carriers in the depletion region cause impact ionization, and generate additional free carriers (electron-hole pairs
320
).
These additional free carriers
320
are swept out of the depletion region by the high electric field. Some of the resulting free holes flow into the P-type substrate region as majority carriers, creating a substrate current Isub that increases with Vds, as illustrated in FIG.
4
. Some of the free electrons are swept into the N-type drain region as majority carriers and add to the drain current Ids. These two charge carrier flows appear as an additional component Isub of the total current in the drain and substrate terminals.
An empirical expression for the impact ionization substrate current Isub is given by,
Isub=K
1
(
Vds B Vdssat
)*
Id
*(exp [−[
K
2
/(
Vds−Vdssat
)]]),
Where K
1
and K
2
are process-dependent parameters and Vdssat is the value of Vds where the drain characteristics enter the saturation region. Under normal operating conditions, MOS devices have essentially zero substrate current Oust the leakage current of the reverse biased drain-to-substrate depletion region), as illustrated in FIG.
4
. The effect is generally much less significant in PMOS devices because the lower mobility holes in the depletion region are less efficient in creating hole-electron pairs than are the higher mobility electrons.
Differentiating this expression with respect to drain voltage, the small signal shunt conductance (g
db
) from drain to substrate is given as,
g
db
=K
2
[I
SUB
]/(
Vds−Vd
sat
){circumflex over ( )}, 2.
Substituting for I
SUB
with the previous expression and rearranging factors produces:
g
db
=K
2
K
1
(
Vds−Vdssat
)
−1
(exp[−[
K
2
/(
Vds−Vdssat]].
FIG. 2
illustrates a plot of g
db
and its inverse, r
db
, for a typical NMOS transistor. r
db
is the equivalent substrate current drain-to-body output resistor that would combine in parallel with the normal transistor output resistance r
0
. r
db
is calculated for a typical NMOS transistor with K
1
=5 V{circumflex over ( )}−1 and K
2
=30 V and plotted vs. normalized drain-source voltage, Vds−Vdssat. Also plotted is the equivalent output conductance, g
db
, which is the inverse of r
db
. The extreme nonlinear behavior of Isub causes the parallel combination of r
db
and r
0
to be essentially r
0
at drain voltages around Vdssat and below, since r
db
is many orders of magnitude greater than typical r
0
.
However, at instantaneous drain-to-source voltages not much higher than a few times Vdssat, the output impedance of the transistor can be completely dominated by r
db
. This is one example of how instantaneous or cumulative changes in hot-electron induced substrate current can influence the magnitude and/or variability of device characteristics. This influence can limit and sometimes defeat the possibility of achieving or maintaining desired performance circuit functionality.
As the instantaneous drain-to-source voltage of the transistor varies during operation, the instantaneous amount of the substrate current also varies causing variation of the small signal output conductance. Depending on the operating point and the output voltage swing of the cascode circuit (between the maximum required output voltage and the minimum possible output voltage), the substrate current Isub can vary dramatically. Isub can vary from a value essentially equal to zero at low and moderate Vds to a value that represents a significant portion of the total drain current as the instantaneous Vds approaches the maximum required output voltage or exceeds a critical value. The critical value of Vds (Vds=Vcrit) for the onset of significant Isub (i.e., Vds=Vcrit) depends on the available power supply voltage, the particular circuit function and performance factor(s) at issue, the transistor technology, the transistor dimensions (primarily channel length), and the bias and signal levels. Highly nonlinear circuit behavior may occur depending on the level of the output voltage. If the substrate current magnitude or the magnitude of current variation is substantial compared to the expected drain current or normal drain current variation, it may adversely effect circuit functional performance, behavior and reliability.
This critical value Vcrit depends on the details of the transistor construction, the magnitude of the instantaneous differences between drain, gate, source and substrate voltages and the drain current. The magnitude of the substrate current is a highly nonlinear function of the voltage differences and current, and can vary by orders of magnitude over very small changes in the instantaneous terminal voltages. The substrate current is affected most by the drain-to-source voltage Vds once Vds approaches Vcrit for the particular transistor technology, geometry and circuit voltage conditions.
The performance of a circuit may be affected by this radically nonlinear Isub behavior primarily in two ways. First, radical variation of I
SUB
may limit one or more selected characteristics of circuit performance (bias current, switching voltage threshold, switching time delay, gain, distortion, noise, and the like). A momentary increase in I
SUB
at a high Vds voltage above critical value Vcrit causes an unacceptable momentary change in an electrical device parameter from its nominal design value. Second, cumulative changes or drifts in a device electrical parameter e.g., parameters such as threshold voltage, transconductance, leakage current and the like may affect circuit performance. Sufficient shifts in device parameters may cause a consequent reduction of the Mean-Time-to-Failure (MTBF) for circuits of a given type, i.e. decreased reliabili
Cadence Design Systems Inc.
Mottola Steven J.
Schipper John
Steres George M.
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