Voltage limiter circuit

Details Voltage limiter circuit Voltage limiter circuit

1994-09-29

1998-03-24

Wong, Peter S.

Electricity: power supply or regulation systems

Input level responsive

455 72, 327310, 333 14, 381106, G05F 500

Patent

active

057316953

ABSTRACT:
First and second analogue signal processing circuit has first to fourth input terminals and first and second output terminals, and functions such that the first and second output terminals have an equal potential and that a difference between output currents of the first and second output terminals is proportional to a product obtained by multiplying a potential difference between the first and second input terminals by a potential difference between the third and fourth input terminals. The first input terminal of the first analogue signal processing circuit is supplied with an input signal, and the second input terminal is supplied with ground potential. The third input terminal is supplied with a second reference potential, and the fourth input terminal is supplied with a third reference potential. The first input terminal of the second analogue signal processing circuit is supplied with an output signal from an operational amplifier, and the second input terminal is supplied with the ground potential. The third input terminal is supplied with the second reference potential, and the fourth input terminal is supplied with a potential outputted from a potential generator circuit. The first and second output terminals of the second analogue signal processing circuit are respectively connected to negative and positive input terminals of the operational amplifier. The operation amplifier has an output terminal and negative and positive input terminals respectively supplied with output potentials from the first and second output terminals of the first analogue signal processing circuit.

REFERENCES:
patent: 4642583 (1987-02-01), Fucito et al.
patent: 4701722 (1987-10-01), Dolby
patent: 5023490 (1991-06-01), Gittinger
patent: 5293139 (1994-03-01), Polonen et al.
Shioda, S. et al., "1.8V CMOS Analog Compander with 80dB Dynamic Range", CCIC '93, pp. 1.1-1.4.
Okamura, "Design of OP Amplifier Circuit, Revised Edition", CQ Shuppan-Sha, Aug. 10, 1973, pp. 179-189.

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