Voltage level triggered ESD protection circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control

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327 78, 327143, 361 56, H02H 904

Patent

active

055086497

ABSTRACT:
A voltage level triggered ESD protection circuit is immune to standard signal transitions up to approximately 5.5 volts, does not consume any DC current either in the powered up or powered down states, and is interfaceable to a live bus when the system it is connected to is powered down. The trigger circuit is reliably immune to tripping from applied fast bus transitions on a powered-down integrated circuit. The trigger signal is generated in response to sensing both a voltage transition and to reaching a voltage set point such as 7 volts, rather than merely triggering off the voltage transition.

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United States SIR, Piasecki, Registration No. H497, Published Jul. 5, 1988.

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