Voltage level shifting depletion mode FET logical circuit

Details Voltage level shifting depletion mode FET logical circuit Voltage level shifting depletion mode FET logical circuit

1985-09-19

1987-05-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307481, 307246, H03K 19017

Patent

active

046635432

ABSTRACT:
A GaAs D-MESFET logic system having a low power delay product has a switching second and a voltage level shifting section. The voltage level shifting section consists of a chain of diodes and a pulldown transistor. The switching section consists of an array of D-MESFETs which acts to speed up operation of a coupling capacitor. The low power dissipation of known capacitor coupled D-MESFET logic is thus preserved, while reducing gate delay.

REFERENCES:
patent: 3845324 (1974-10-01), Feucht
patent: 4558235 (1985-12-01), White et al.
patent: 4574209 (1986-03-01), Lade et al.
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Reading, Mass., Oct. 1980, pp. 17-18.
Zuleeg et al., "Femtojoule High-Speed Planar GaAs E-JFET Logic", IEEE T.E.D., vol. ED-25, No. 6, Jun. 1978, pp. 626-639.
Furman et al., "Inverter Driver with Improved Performance", IBM TDB, vol. 23, No. 8, Jan. 1981, p. 3612.

Affiliated with

Also associated with

Rating

Voltage level shifting depletion mode FET logical circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage level shifting depletion mode FET logical circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage level shifting depletion mode FET logical circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2400736