Voltage level shifter implemented by essentially PMOS...

Details Voltage level shifter implemented by essentially PMOS... Voltage level shifter implemented by essentially PMOS...

2005-07-26

2005-07-26

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S112000

Reexamination Certificate

active

06922095

ABSTRACT:
A voltage level shifter includes a front stage circuit periodically generating a first control signal and a second control signal in response to a first input clock signal and a second input clock signal complementary to the first input clock signal; a switch circuit including two PMOS transistors connected between a maximum voltage and a minimum voltage in series, wherein a third control signal is outputted from a conjunction of the two PMOS transistors, and the first and second control signals are coupled to the gate electrodes of the two PMOS transistors, respectively; and a driving circuit receiving the third control signal and outputting an output clock signal having a peak-to-peak value larger than a peak-to-peak value of the input clock signal. The voltage level shifter is implemented by essentially PMOS transistors.

REFERENCES:
patent: 6756835 (2004-06-01), Yu
patent: 2002/0158666 (2002-10-01), Azami et al.

Affiliated with

Also associated with

Rating

Voltage level shifter implemented by essentially PMOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage level shifter implemented by essentially PMOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage level shifter implemented by essentially PMOS... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3398345