Voltage level shifter and phase splitter

Details Voltage level shifter and phase splitter Voltage level shifter and phase splitter

2001-11-21

2002-11-05

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S081000

Reexamination Certificate

active

06476659

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a high speed voltage shifter and phase splitter circuit.
DESCRIPTION OF THE RELATED ART
FIGS. 1 and 2
together illustrate a prior art voltage level shifter for providing first and second phase outputs. In
FIG. 1
, an input voltage A
1
IN is applied to the voltage level shifter to produce a first phase output D. In
FIG. 2
, an input voltage A
21
N is applied to the voltage level shifter to produce a second phase output D
2
. The input voltage A
1
IN and the input voltage A
21
N are out of phase with each other.
Referring to both
FIGS. 1 and 2
, the respective input voltages A
1
IN and A
21
N are applied to input inverter stages coupled to a first voltage supply VDD. Node B
2
is inverter delayed by a single inverter stage formed of P-channel field effect transistor (PFET) P
1
and an N-channel field effect transistor (NFET) N
1
and out of phase to A
1
IN in
FIG. 1
or A
21
N in FIG.
2
. Node BBB
2
is buffer delayed by a pair of parallel inverters formed by P
2
, N
2
and P
3
, N
3
and is in phase with A
1
IN in
FIG. 1
or A
21
N in FIG.
2
. The input inverters NFETs N
1
and N
3
are connected to a common node labeled NET
3
and to a respective pair of NFETs N
5
, N
6
and N
7
, N
8
. Node NET
3
is coupled to a second voltage supply VDDQ via a pair of NFETs N
9
, N
10
. Output inverter stages formed of P
11
, N
11
, and P
12
, N
12
coupled between a second voltage supply VDDQ via a pair of PFETs P
13
, P
14
and ground via a pair of NFETs N
13
, N
14
. PFET P
13
is always turned on by a low enable input ENBAR applied to the gate input. NFET N
14
is always turned on by a high enable input ENN applied to the gate input. NFETs N
6
and N
8
are turned on by a high enable input ENN applied to the gate input, which together with NFETs N
5
and N
7
help to pull node NET
3
low. Output inverter stages formed of P
11
, N
11
, and P
12
, N
12
respectively receive a gate input of BBB
2
and B
2
.
FIGS. 4
,
5
, and
6
illustrate voltage waveforms of the prior art voltage level shifter of
FIGS. 1 and 2
with voltage shown relative the vertical axis and time shown relative to the horizontal axis. In
FIG. 4
, voltage waveforms A
1
IN, B
2
, BBB
2
, and NET
3
are illustrated.
FIG. 5
provides an expanded view of the voltage waveforms A
1
IN, B
2
, BBB
2
, and NET
3
of FIG.
4
.
FIG. 6
illustrates the input voltage waveform A
1
IN together with outputs D and D
2
of
FIGS. 1 and 2
. The prior art level shifter has an operational time delay that is much greater than can be used effectively for high speed applications. Another problem with the prior art level shifter is that balanced output is not provided. As illustrated in
FIG. 6
, with VDDQ of 1.5 Volts, the cross point of outputs D and D
2
is at about 1.07 Volts, rather than VDDQ/
2
or 0. 75 Volts.
A need exists for an improved high speed voltage shifter and phase splitter circuit. It is desirable to provide such a voltage shifter and phase splitter circuit that achieves balanced outputs as well as a small delay. It is also desirable to provide such a voltage shifter and phase splitter circuit that minimizes the number of devices required to produce two phases so that less physical area is required.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an improved high speed voltage shifter and phase splitter circuit. Other important objects of the present invention are to provide such voltage shifter and phase splitter circuit substantially without negative effect and that overcomes many of the disadvantages of prior art arrangements.
In brief, a high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal. A first input inverter stage receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.


REFERENCES:
patent: 5453707 (1995-09-01), Hiratsuka et al.
patent: 5559464 (1996-09-01), Orii et al.
patent: 6002290 (1999-12-01), Avery et al.
patent: 6020779 (2000-02-01), Udo
patent: 6046621 (2000-04-01), Crowley
patent: 6323711 (2001-11-01), Truong et al.

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