Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-10-18
2002-07-09
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S071000
Reexamination Certificate
active
06417700
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology of detecting the voltage level of an analog signal transmitted through a cable.
FIG. 9
shows a construction of a conventional transmit/receive circuit. The transmit/receive circuit of
FIG. 9
, which complies with the IEEE 1394 standard, for example, transmits/receives transmission rate information for data using the voltage level at a signal transmission line such as a cable
51
. The IEEE 1394 standard specifies a differential signal for transmitting data and an in-phase signal for transmitting a transmission rate for the data. In the construction shown in
FIG. 9
, transmission/reception of a differential signal (data signal) is performed between a driver
52
a
,
52
a
and a receiver
53
a
,
53
b
, while an in-phase signal (speed signal) is transmitted by a speed signal driver
54
and received by a speed signal receiver
55
.
The speed signal driver
54
drives a cable potential by drawing a current by an amount corresponding to the data transmission rate from the cable
51
for a predetermined time period, to thereby generate a speed signal as shown in FIG.
10
. On the receiver side, the speed signal receiver
55
converts the received speed signal to digital signals of several bits by comparing the change amount of the cable potential with predetermined reference potentials using a plurality of comparators. The resultant digital signals are handed over to a later-stage logic circuit for processing.
The conventional technique described above has the following problem.
FIG. 11
is a timing chart showing the relationship between an analog signal ADin received by the speed signal receiver
55
and digital signals ADout
1
and ADout
2
obtained by converting the analog signal ADin. As shown in
FIG. 11
, the change in the voltage level of the analog signal ADin is not sharp but is slowed due to the resistance and parasitic capacitance of the cable, the characteristics of the speed signal driver
54
, and the like. For this reason, the digital signals ADout
1
and ADout
2
have pulse widths largely different from each other. This generates a time region in which the digital signal ADout
1
has already risen but the digital signal ADout
2
has not yet risen, or a time region in which the digital signal ADout
2
has already fallen but the digital signal ADout
1
has not yet fallen. Such a time region is herein called an uncertain region G.
If a later-stage logic circuit retrieves the digital signals ADout
1
and ADout
2
during this uncertain region G, malfunction may occur in voltage level detection. In other words, the existence of the uncertain region G as shown in
FIG. 11
is disadvantageous because it may cause erroneous detection of the voltage level of the analog signal ADin.
SUMMARY OF THE INVENTION
An object of the present invention is preventing malfunction in voltage level detection during detection of the voltage level of an analog signal.
The circuit for detecting the voltage level of an analog signal of the present invention includes: a conversion circuit for comparing the voltage level of the analog signal with a plurality of different reference potentials and converting the analog signal to a plurality of digital signals based on the comparison result; and a filter circuit for filtering the plurality of digital signals output from the conversion circuit, wherein the filter circuit matches timings of at least one of rising edges and falling edges of at least two of the plurality of digital signals with each other.
According to the invention described above, in the conversion circuit, a plurality of digital signals are obtained by comparing the voltage level of an analog signal with a plurality of reference potentials. When the change of the analog signal is not sharp, the resultant digital signals may be different in pulse width, and this may possibly cause generation of an uncertain region. To overcome this problem, the filter circuit matches timings of either the rising edges or the falling edges of at least two of the plurality of digital signals with each other. By this operation, there exists no uncertain region at the edges of which timings have matched with each other. Therefore, possible malfunction in voltage level detection can be prevented.
The filter circuit preferably includes a RS flipflop for receiving an inverted signal of a first digital signal among the plurality of digital signals as reset input and a second digital signal among the plurality of digital signals as set input.
Alternatively, the circuit for detecting the voltage level of an analog signal of the present invention includes: a conversion circuit for comparing the voltage level of the analog signal with a plurality of reference potentials including at least a first reference potential and a second reference potential lower than the first reference potential, and converting the analog signal to a plurality of digital signals based on the comparison result, wherein the conversion circuit comprises: a first comparator for comparing the voltage level of the analog signal with the first reference potential; a selector for selecting and outputting one of the first and second reference potentials; and a second comparator for comparing the voltage level of the analog signal with the reference potential selected and output from the selector, and wherein the selector receives an output of the second comparator as a selection signal, and selects and outputs the first reference potential when the selection signal indicates that the voltage level of the analog signal is lower than the reference potential, and selects and outputs the second reference potential when the selection signal indicates that the voltage level of the analog signal is higher than the reference potential.
According to the invention described above, in the conversion circuit, when the voltage level of the analog signal falls below the second reference potential, the selector selects and outputs the first reference potential based on the output of the second comparator. In other words, both the first and second comparators perform comparison using the first reference potential until the voltage level of the analog signal reaches the first reference potential, and thus output the same comparison result. Therefore, the digital signals corresponding to the first and second comparators match with each other at the timings of the edges corresponding to the end of a change of the voltage level of the analog signal. No uncertain region exists at the edges of which timings have matched with each other. Thus, possible malfunction in voltage level detection can be prevented.
Alternatively, the circuit for detecting the voltage level of an analog signal of the present invention includes: a conversion circuit for comparing the voltage level of the analog signal with a first reference potential and a second reference potential, and converting the analog signal to first and second digital signals based on the comparison result; and a sample-hold circuit for receiving the first and second digital signals and outputting first and second hold signals representing the voltage level of the analog signal, wherein, in a case where the logical level of the first digital signal changes, the sample-hold circuit holds the first hold signal at one logical level when the logical level of the second digital signal does not change, and holds the second hold signal at the one logical level when the logical level of the second digital signal changes.
According to the invention described above, in the sample-hold circuit, the first or second hold signal is held at one logical level depending on the change of the logical level of a digital signal. This further increases the time period allowed for signal retrieval by the later-stage logic section, and thus improves the precision in voltage level detection.
According to another aspect of the invention, the method for detecting the voltage level of an analog signal includes the steps of: (a) comparing the voltage level of the analog
Akamatsu Hironori
Hirata Takashi
Komatsu Yoshihide
Sugimoto Hirokazu
Takahashi Satoshi
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Nu Ton My-Trang
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