Voltage level converting circuit

Details Voltage level converting circuit Voltage level converting circuit

2001-10-01

2003-05-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000

Reexamination Certificate

active

06559691

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2001-162987, filed on May 30, 2001, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor circuit, and is particularly suitably applicable to a semiconductor circuit for converting an input signal into different levels of signals for output.
Description of the Related Art
Conventionally, there have been some semiconductor integrated circuits which use a power supply voltage and a voltage different from the power supply voltage. Such memory circuits as a dynamic random access memory (DRAM) and a flash memory have supplied their word lines with a high voltage different from the power supply voltage.
For example, in a DRAM, memory cells have a lower threshold voltage V
TH
if they are composed of N-channel transistors. Therefore, a high voltage above the power supply voltage is supplied to word lines to read stored data from the memory cells. To take another example, a flash memory supplies a high voltage above the power supply voltage (for instance, a voltage of 5 to 6 V in the case of a power supply voltage of 2 V) to its word lines, bit lines, and source lines to rewrite (erase and write) data to be stored into memory cells.
These semiconductor integrated circuits using a voltage different from their power supply voltage contain switching circuits as shown in
FIG. 5
, thereby switching the signal levels of predetermined signals to voltage levels different from the power supply voltage.
FIG. 5
is a diagram showing the configuration of a switching circuit to be implemented in a conventional semiconductor integrated circuit.
In
FIG. 5
, the reference numeral
51
designates an input terminal for inputting an input signal IN,
52
an output terminal for outputting an output signal OUT
1
, and
53
an output signal voltage supply terminal for supplying an output signal voltage V
H
different from a power supply voltage VCC (V
H
>VCC). The reference numerals
54
and
55
designate N-channel transistors (hereinafter, referred to a N-channel transistor as “Nch-Tr”), and the numerals
56
and
57
P-channel transistors (hereinafter, referred to a P-channel transistor as “Pch-Tr”).
The input terminal
51
is connected to the gate of the Nch-Tr
54
and the source of the Nch-Tr
55
. The Nch-Tr
54
is connected at its source to a reference voltage VSS (in
FIG. 5
, a ground potential). The Nch-Tr
55
is connected at its gate to the power supply voltage VCC. The drain of the Nch-Tr
54
and the drain of the Pch-Tr
56
are connected with each other. To the interconnection node, the output terminal
52
and the gate of the Pch-Tr
57
are connected.
The drain of the Nch-Tr
55
and the drain of the Pch-Tr
57
are connected to each other. To the interconnection node is connected the gate of the Pch-Tr
56
. In addition, the source of the Pch-Tr
56
and the source of the Pch-Tr
57
are connected to the output signal voltage supply terminal
53
.
In the switching circuit shown in
FIG. 5
described above, an input signal IN carrying the power supply voltage VCC (high level) is input through the input terminal
51
to turn ON the Nch-Tr
54
. This lowers the potential of the interconnection node between the drain of the Nch-Tr
54
and the drain of the Pch-Tr
56
, turning ON the Pch-Tr
57
which is connected at its gate to the interconnection node. This turns OFF the Pch-Tr
56
which is connected at its gate to the drain of the Pch-Tr
57
. Accordingly, when the input signal IN carrying the power supply voltage VCC (high level) is input, the Nch-Tr
54
turns ON and the Pch-Tr
56
turns OFF so that an output signal OUT
1
carrying the reference voltage VSS (low level) is output through the output terminal
52
.
On the other hand, an input signal IN carrying the reference voltage VSS (low level) is input through the input terminal
51
to turn OFF the Nch-Tr
54
. This also lowers the potential of the interconnection node between the drain of the Nch-Tr
55
and the drain of the Pch-Tr
57
, turning ON the Pch-Tr
56
which is connected at its gate to the interconnection node. The Pch-Tr
57
accordingly turns OFF. Therefore, when the input signal IN carrying the reference voltage VSS (low level) is input, the Nch-Tr
54
turns OFF and the Pch-Tr
56
turns ON so that an output signal OUT
1
carrying the output signal voltage V
H
(high level) is output through the output terminal
52
.
In this way, the switching circuit shown in
FIG. 5
has switched the signal level of a signal input from the power supply voltage level to the output signal voltage level different from the power supply voltage for output.
In the conventional switching circuit shown in
FIG. 5
, however, the Nch-Tr
54
and the Pch-Tr
56
temporarily coincide in an ON state when the input signal IN changes from the reference voltage VSS (low level) to the power supply voltage VCC (high level). On that account, the switching circuit described above deteriorates in switching characteristics, requiring a great deal of time before the output signal OUT
1
output from the switching circuit changes from the output signal voltage V
H
(high level) to the reference voltage VSS (low level).
Moreover, in the switching circuit shown in
FIG. 5
, the transistor size ratio between the Nch-Tr
54
and the Pch-Tr
56
constituting this switching circuit has a profound effect on the switching characteristics. Therefore, to improve the switching characteristics of the switching circuit, it is required that the Nch-Tr and Pch-Tr be designed after determination of an optimum transistor size ratio. Nevertheless, even if the optimum transistor size ratio between the Nch-Tr and Pch-Tr is determined and the switching circuit is designed accordingly, the switching circuit can deviate in switching characteristics when the power supply voltage VCC and the output signal voltage V
H
have greater amplitudes. For this reason, the switching characteristics have been difficult to control.
For a solution to such problems, there has been a method of adopting a switching circuit as shown in
FIG. 6
for a semiconductor integrated circuit using a voltage different from the power supply voltage, so that the signal level is switched from the power supply voltage level to a voltage level different from the power supply voltage.
FIG. 6
is a diagram showing another configuration of the switching circuit to be implemented in a conventional semiconductor integrated circuit.
In
FIG. 6
, the reference numerals
64
,
66
, and
69
designate Nch-Trs, and
67
,
68
, and
70
Pch-Trs. The Nch-Trs
64
,
66
, and
69
are connected to a reference voltage VSS (ground potential) at their respective sources. The Pch-Trs
67
,
68
, and
70
are connected at their respective sources to an output signal voltage supply terminal
63
for supplying an output signal voltage V
H
(V
H
>power supply voltage VCC). An input terminal
61
for inputting an input signal IN is connected to the gate of the Nch-Tr
64
and the input of an inverter
65
. The output of the inverter
65
is connected to the gate of the Nch-Tr
66
.
The drain of the Nch-Tr
64
and the drain of the Pch-Tr
67
are connected to each other. The gate of the Pch-Tr
68
is connected to the interconnection node. Similarly, the drain of the Nch-Tr
66
and the drain of the Pch-Tr
68
are connected to each other. To the interconnection node is connected the gate of the Pch-Tr
67
. That is, the Nch-Trs
64
and
66
, the Pch-Trs
67
and
68
, and the inverter
65
constitute a level shift circuit in which an input signal IN input through the input terminal
61
is shifted to the output signal voltage V
H
in signal level and output with its logic kept intact.
The interconnection node between the drain of the Nch-Tr
66
and the drain of the Pch-Tr
68
is also connected with the gate of the Nch-Tr
69
and the gate of the Pch-Tr
70
. The drain of the Nch-Tr
69
and the drain of t

Affiliated with

Also associated with

Rating

Voltage level converting circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage level converting circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage level converting circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3002212