Voltage level converters

Details Voltage level converters Voltage level converters

1999-03-19

2001-05-22

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S062000, C327S068000

Reexamination Certificate

active

06236256

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates to voltage level converters, and is useful in inter alia high speed CMOS circuits which receive many data inputs at a voltage significantly less than the supply voltage. The invention is of particular use in the field of monolithic digital data drivers for active matrix displays. In these circuits low performance TFT circuitry requires a high supply voltage to achieve the necessary speed of operation, whereas to minimise power consumption low voltage inputs are desirable.
DESCRIPTION OF THE RELATED ART
The simplest. type of prior art digital level shifter is shown in
FIG. 1
, and described in detail in A. Bellaouar, M. Elmasry.
Low Power Digital VLSI Design
. Kluwer Academic Publishers, 1995. The circuit consists of two CMOS inverters
2
and
4
, each comprising a p-type (PMOS) transistor M
1
, M
3
and an n-type (NMOS) transistor M
2
, M
4
. The first CMOS inverter
2
is powered by a supply voltage VDD
1
, and the second CMOS inverter
4
is powered by a larger supply voltage VDD
2
. The main disadvantage of this circuit is that the power consumption is considerable since both transistors M
3
and M
4
in the second inverter
4
conduct when the output of the first inverter
2
is high, ie. equal to VDD
1
. One of the basic criteria for minimising power consumption is that there should be no direct current path between the supply voltages and ground.
A further prior art circuit is shown in
FIG. 2
, and described in detail in U.S. Pat. No. 4,486,670. This circuit overcomes the problem of direct power consumption by using a latch (consisting of the four transistors M
5
, M
6
, M
7
and M
8
) to ensure that if one of the complementary transistors M
3
or M
4
is turned on, the other is turned off.
A widely used level shift circuit with improved latching action is shown in the prior art circuit of
FIG. 3
, and described in detail in U.S. Pat. No. 4,845,381. Two CMOS inverters
6
and
8
, made up of transistors M
1
, M
2
and M
4
, M
5
respectively, receive complementary digital input signals INPUT and INPUT*, varying between voltages of VDD
1
and GND. The outputs
9
and
11
of the inverters
6
and
8
are cross-coupled and applied to the gates of the p-type transistors M
3
and M
6
which control the supply of a higher voltage VDD
2
to the inverters
6
and
8
. If the input signal INPUT is at VDD
1
(ie. logic high) and the complementary input INPUT* is at ground, then transistors M
1
, M
5
and M
6
are on whilst transistors M
2
, M
3
and M
4
are off. Thus the output
13
of the shift circuit as a whole is at voltage VDD
2
(ie. logic high). The main limitation of this approach for large numbers of inputs is the need to supply two complementary input signals.
SUMMARY OF THE INVENTION
According to the invention there is provided a voltage level converter for converting an input signal at a first voltage level to an output signal at a second voltage level, the converter comprising an input for receiving said input signal, an output for outputting said output signal, a circuit node, precharge means for charging or discharging said circuit node to a third voltage level during a first time period by connection of said circuit node to a first voltage supply, isolation means for isolating said circuit node from said first voltage supply during a second time period, input means for changing the voltage at said circuit node in dependence on the voltage at said input during a third time period, and output means arranged so that the voltage at said output depends on the voltage at said circuit node.
Such a level converter does not require a complementary input signal, which is particularly advantageous if a number of such level converters are used in an arrangement having a large number of inputs. In addition, the isolation means can be used to prevent a direct current path from the first voltage supply to ground, thus reducing power consumption.
Said third voltage level may be substantially equal to said second voltage level.
This allows said first voltage supply to be used for both said output signal and for charging or discharging said circuit node.
Said third time period may coincide with, or lie within, said second time period.
The voltage level converter may further comprise an input node which is charged or discharged to a fourth voltage level during said first time period by connection of said input node to a second voltage supply.
Said isolation means may isolate said input node from said second voltage supply during said second time period.
Said second voltage supply may be negatively biased with respect to said input signal.
Said isolation means may comprise a first isolation field effect transistor the source and drain of which are connected between said second voltage supply and said input node.
Said isolation means may comprise a second isolation field effect transistor the source and drain of which are connected between said first voltage supply and said circuit node.
Said input means may comprise a sampler for sampling said input signal during said third time period.
Said sampler may comprise a sampling field effect transistor the gate of which is connected to a sampling signal.
The source and drain of said sampling field effect transistor may be connected between said input and said input node.
The voltage level converter may further comprise a latch for latching said output signal at the voltage determined by said input means.
The voltage level converter may further comprise a feedback field effect transistor, the source and drain of which are connected between said first voltage supply and said input node, and the gate of which is connected to said circuit node.
This provides the advantage of increased switching speed of the level converter, by increasing the switching speed of the input transistor mentioned below.
Said output means may comprise a CMOS inverter, the input of which is connected to said circuit node.
Said input means may comprise an input field effect transistor arranged to discharge said circuit node if said input signal is at a logic high level during said third time period.
The source and drain of said input field effect tristor may be connected between said circuit node and said second voltage supply, and the gate of said input field effect transistor may be connected to said input node.
The source of said input field effect transistor may be connected to said second voltage supply.
This provides the advantage that, if said second voltage supply is negatively biased with respect to said input signal, the drive efficacy of the input signal is increased.
The gate of said input field effect transistor may be connected to said negative voltage supply during said first time period, and isolated from said negative supply during said second time period.
Said input and output signals may be digital signals.
The invention also provides an active matrix liquid crystal display comprising a voltage level converter as described above.


REFERENCES:
patent: 3835457 (1974-09-01), Yu
patent: 3925689 (1975-12-01), Rubenstein
patent: 5099143 (1992-03-01), Arakawa
patent: 5457420 (1995-10-01), Asada
patent: 5818280 (1998-10-01), Martin
patent: 0215288A1 (1987-03-01), None
patent: 0215280A1 (1987-03-01), None
patent: 0218940A1 (1987-04-01), None
patent: 1263128 (1972-02-01), None
patent: 1514964 (1978-06-01), None
patent: 402134918 (1990-05-01), None
patent: 403157011 (1991-07-01), None
GB 9805882.9 Search Report.

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