Voltage level compensating interface circuit for inter-logic cir

Details Voltage level compensating interface circuit for inter-logic cir Voltage level compensating interface circuit for inter-logic cir

1985-04-26

1986-01-28

Thomas, James D.

Boots, shoes, and leggings

307475, 365189, G06F 304

Patent

active

045675759

ABSTRACT:
An interface circuit is disposed between an NMOS random access memory and a PMOS central processor unit in order to ensure accurate data transfer therebetween. The interface circuit includes a pull-up system for pulling up a signal transmission line to a desired voltage level. The pull-up system is energized when the data signal is transferred from the NMOS random access memory into the PMOS central processor unit. The pull-up operation is not conducted when the data signal is transferred from the PMOS central processor unit into the NMOS random access memory.

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