Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1975-06-05
1977-08-16
Miller, Jr., Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307304, 323 22R, H03K 1700
Patent
active
040428435
ABSTRACT:
A particular voltage level in an integrated MOS chip is maintained by defining that level as an integral multiple of drain-to-gate voltage thresholds and by actively controlling that level in response to deviations therefrom. Plural MOSFET elements are connected in circuit so that their drain-to-gate capacitances are serially effective across internal signal lines (e.g. busses) for bias so as to establish a reference level to be compared with the actual voltage on these signal lines; and through feedback the signal level as applied from outside of the chip to these lines or busses is reduced to obtain the desired multiple threshold voltage as operating voltage on these lines for use by other elements in the chip.
REFERENCES:
patent: 3657575 (1972-04-01), Taniguchi et al.
patent: 3808468 (1974-04-01), Ludlow et al.
patent: 3823332 (1974-07-01), Feryszka et al.
patent: 3881041 (1974-08-01), Krambeck et al.
FET Device Parameter Compensation Circuit by Askin et al., IBM Tech. Bultn., vol. 4, No. 7, 12/71, p. 2088.
Davis B. P.
Electronic Arrays, Inc.
Miller, Jr. Stanley D.
Siegemund Ralf H.
LandOfFree
Voltage level adaption in MOSFET chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Voltage level adaption in MOSFET chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage level adaption in MOSFET chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-363342