Voltage keeping scheme for low-leakage memory devices

Details Voltage keeping scheme for low-leakage memory devices Voltage keeping scheme for low-leakage memory devices

2006-06-13

2006-06-13

Mai, Son (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S189090, C365S226000

Reexamination Certificate

active

07061820

ABSTRACT:
The present invention facilitates memory device operation by mitigating power consumption during suspend modes of operation, also referred to as sleep/data retention modes. This is accomplished by employing one or more gate-sinking voltage keeper components that operate as leakage current sinks during the suspend mode of operation instead of gate-sourcing voltage keeper components that operate as leakage current sources during the suspend mode of operation, on a circuit node whose voltage level is maintained by a sinking voltage regulator. As a result, less leakage current is required to be dissipated/sunk by a voltage regulator and/or other circuit paths or components of the memory device. Thus, relatively less power is consumed.

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