Voltage interfacing buffer with isolation transistors used for o

Details Voltage interfacing buffer with isolation transistors used for o Voltage interfacing buffer with isolation transistors used for o

1992-11-10

1994-04-05

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307473, 3072965, H03K 190185, H03K 19003

Patent

active

053008324

ABSTRACT:
A voltage interfacing buffer for interfacing a low voltage integrated circuit to a high voltage environment, wherein the integrated circuit contains only low voltage transistors. To drive the high voltage environment at the low voltage swing, the voltage interfacing circuit employs protection circuits and novel n-well biasing of MOS transistors. To drive the high voltage environment at the high voltage swing, the voltage interfacing circuit employs a bias generator circuit to bias buffer transistors supplied with the high voltage. As example applications, the voltage interfacing buffer enables a 3 volt or 3.3 volt integrated circuit chip to drive TTL as well as CMOS voltage levels. Moreover, the voltage interfacing buffer enables a 2 volt integrated circuit chip to drive TTL voltage levels.

REFERENCES:
patent: 4709162 (1987-11-01), Braceras et al.
patent: 4782250 (1988-11-01), Adams et al.
patent: 4825102 (1989-04-01), Iwasawa et al.
patent: 4920287 (1990-04-01), Hartgring et al.
patent: 4963766 (1990-10-01), Lundberg
patent: 4996443 (1991-02-01), Tateno
patent: 5019720 (1991-05-01), Skoog et al.
patent: 5128560 (1992-07-01), Chern et al.

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