Static information storage and retrieval – Powering
Reexamination Certificate
1999-02-23
2001-07-24
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Powering
C365S189090
Reexamination Certificate
active
06266291
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuit devices, and more particularly, to antifuse and fuse reading circuits in integrated devices.
BACKGROUND OF THE INVENTION
Typical integrated memory circuits include arrays of memory cells arranged in rows and columns. In many such integrated memory arrays, several redundant rows and columns are provided to be used as substitutes for defective locations in memory. When a defective location is identified, rather than treating the entire array as defective, a redundant row or column is substituted for the defective row or column. This substitution is performed by assigning the address of the defective row or column to the redundant row or column such that, when an address signal corresponding to the defective row or column is received, the redundant row or column is addressed instead.
To make substitution of the redundant row or column substantially transparent to a system employing the memory circuit, the memory circuit includes an address detection circuit. The address detection circuit monitors the row and column addresses and, when the address of a defective row or column is received, enables the redundant row or column instead.
One type of address detection circuit is a fuse-bank address detection circuit. Fuse-bank address detection circuits employ a bank of sense lines where each sense line corresponds to a bit of an address. The sense lines are programmed by blowing fuses in the sense lines in a pattern corresponding to the address of the defective row or column. Addresses are then detected by first applying a test voltage across the bank of sense lines. Then, bits of the address are applied to the sense lines. If the pattern of blown fuses corresponds exactly to the pattern of address bits, the sense lines all block current and the voltage across the bank remains high. Otherwise, at least one sense line conducts and the voltage falls. A high voltage thus indicates the applied address corresponds to a defective row or column.
An alternative address detection circuit employs antifuses in place of conventional fuses. Antifuses are capacitive-type structures that, in their unblown states, form open circuits. Antifuses may be “blown” during programming by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Therefore, blown antifuses conduct and unblown antifuses do not conduct. However, due to variations among the individual antifuses, the response to the high-voltage may vary significantly across a particular group. For example, some of the antifuses may blow quickly while other, more robust antifuses may take significantly longer to blow. Consequently, more robust antifuses may be only marginally blown during programming.
Individual antifuses are programmed to form a pattern corresponding to the address of the defective row or column. Generally, the individual antifuses are read by a antifuse reading circuit which generates a digital value or signal indicating whether the antifuse is blown or unblown. The resulting pattern of digital values provides the address of the defective row or column. When a memory device is accessed, the individual antifuses are read and a resulting pattern of the antifuses is compared with an incoming address. If the addresses match, the address detection circuit generates a match signal indicating that the address programmed by the antifuses has been detected. As a result, a redundant row or column is accessed instead of the defective location.
Shown in
FIG. 1
is a subsystem
100
of a memory device having a conventional antifuse reading circuit
106
that can be used to read an antifuse
130
, and generate a FUSE* signal indicating the blown or unblown state of the antifuse
130
. Several elements of the subsystem
100
that are related to programming the antifuse have been omitted from
FIG. 1
in the interest of brevity, and are not needed in explaining the reading operation of the conventional antifuse reading circuit
106
. An external voltage VCCX is applied to an external terminal
101
. An internal power source
102
receives the VCCX voltage and generates an internally regulated voltage VCCR that is used by the internal circuitry of the memory device. The VCCR voltage is provided to a logic circuit
104
that generates an SV signal used during a fuse reading operation, and is also provided to a node
108
of the antifuse reading circuit
106
. The internal power source
102
is designed to provide a VCCR voltage that is relatively constant over a predetermined voltage range of the VCCX voltage. Although the VCCR voltage is regulated, it will nevertheless increase when the VCCX voltage increases in the predetermined range, but not to the same degree as the VCCX voltage. The design and operation of the internal power source
102
is well known in the art.
The antifuse reading circuit
106
is enabled by an active low signal FP*. The FP* signal is generated by a control circuit (not shown) and is normally high until a fuse read operation is to be initiated. When the FP* signal goes low, a PMOS transistor
110
couples the VCCR voltage to the antifuse
130
through a PMOS transistor
114
, and NMOS transistors
124
,
126
. A gate of the NMOS transistor
124
receives a signal DVC
2
E which is slightly greater than one-half of the VCCR supply, and maintains the NMOS transistor
124
in a conductive state. Similarly, a gate of the NMOS transistor
126
receives a boosted voltage VCCP that exceeds the VCCR voltage, and maintains the NMOS transistor
126
in a conductive state. Therefore, for the purposes of reading the conductive state of the antifuse
130
, the NMOS transistors
124
,
126
will be ON. As mentioned above, when the conductive state of the antifuse
130
is to be read, the logic circuit
104
outputs a high SV signal. The high SV signal turns ON an NMOS transistor
132
, thereby coupling the other terminal of the antifuse
130
to a reference voltage, such as a ground node
134
. The source of the NMOS transistor
132
is normally coupled to a large negative voltage during programming. However, as mentioned above, circuitry for performing this programming will not be shown or explained in the interest of brevity.
If the antifuse
130
is unblown and remains non-conductive, the antifuse
130
will begin charging and a voltage Vn at a node
122
will increase as the antifuse
130
continues to store charge. The voltage Vn will eventually rise above the threshold voltage of an inverter
118
and trigger the inverter
118
to output a low signal. The output of the inverter
118
is in turn inverted by the inverter
120
to produce a high FUSE* signal indicating that the antifuse
130
is unblown. The gate of a PMOS transistor
112
is also coupled to the output of the inverter
118
and is turned ON when the output signal of the inverter
118
goes low to latch the high signal at the node
122
. The PMOS transistor will remain conductive even after the FP* signal returns high to turn OFF the PMOS transistor
110
.
On the other hand, if the antifuse
130
is blown such that it conducts current, the node
122
is essentially coupled through the NMOS transistor
132
to the switchable ground node
134
when the FP* signal goes low, despite the VCCR voltage being applied to the node
122
through the PMOS transistors
110
,
114
. Since the input of the inverter
118
is coupled to the ground node
134
, the inverter
118
will output a high signal, turning off the PMOS transistor
112
, and the inverter
120
will output a low FUSE* signal indicating that the antifuse
130
is blown. When the FP* signal returns high, the node
122
will still be coupled to the ground terminal and thus, the FUSE* signal will remain low.
Problems with the antifuse reading circuit
106
misreading the conductive state of the antifuse
130
may arise when the antifuse
130
is only marginally blown and the VCCR voltage increases above a certain threshold level. A marginally blow
Sher Joseph C.
VanHeel Nick
Dorsey & Whitney LLP
Hoang Huan
Micro)n Technology, Inc.
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