Miscellaneous active electrical nonlinear devices – circuits – and – External effect – Temperature
Reexamination Certificate
2000-07-21
2002-09-17
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
External effect
Temperature
C327S541000
Reexamination Certificate
active
06452437
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-207794, filed July 22, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a voltage generator used for compensating for the temperature dependency of a memory cell current in a nonvolatile semiconductor memory device, for example.
In recent years, a NAND cell type EEPROM is proposed as one type of an electrically rewritable nonvolatile semiconductor memory device (EEPROM).
In the EEPROM, a plurality of memory cells with the n-channel MOSFET structure having, for example, a floating gate as a charge storage layer and a control gate stacked thereon are serially connected by commonly forming the sources and drains of every adjacent two of them, treated as one unit and connected to a bit line.
FIGS. 1A and 1B
are a pattern plan view showing one NAND cell portion extracted from the memory cell array of the NAND cell type EEPROM and an equivalent circuit diagram thereof.
FIGS. 2A and 2B
are cross sectional views respectively taken along the
2
A—
2
A line and
2
B—
2
B line of the pattern of FIG.
1
A.
The memory cell is formed in a p-type well region formed in a n-type well region which is formed in a p-type semiconductor substrate (for example, silicon substrate). A memory cell array formed of a plurality of NAND cells is formed in a portion of a silicon substrate (or p-type well region)
11
which is surrounded by an element isolating oxide film
12
. In this case, attention is given to one NAND cell and it is explained. In this example, eight memory cells M
1
to M
8
are serially connected to construct one NAND cell. Each of the memory cells M
1
to M
8
is formed by forming a floating gate
14
(
14
1
,
14
2
,
14
3
, . . .
14
8
) on the substrate
11
with a gate insulating film
13
formed therebetween and stacking a control gate
16
(
16
1
,
16
2
,
16
3
, . . .
16
8
) on the floating gate
14
with a gate insulating film
15
disposed therebetween. Each n-type diffusion layer
19
(
19
1
,
19
2
,
19
3
, . . .
19
9
) which is used as the source or drain of the memory cell is commonly used by the two adjacent memory cells and thus the memory cells are serially connected.
On the drain side and source side of the NAND cell, first and second selection transistors S
1
, S
2
are respectively formed. The selection transistors S
1
, S
2
have first selection gates
14
9
,
16
9
and second selection gates
14
10
,
16
10
which are respectively formed at the same time as the floating gates and control gates of the memory cells are formed. The selection gates
14
9
,
16
9
are electrically connected to each other in an area which is not shown in the drawing, the selection gates
14
10
,
16
10
are also electrically connected to each other in an area which is not shown in the drawing, and the selection gates are respectively used as the gate electrodes of the selection transistors S
1
, S
2
. A portion of the substrate in which elements are formed is covered with a CVD oxide film
17
and a bit line
18
is formed on the CVD oxide film. The control gates
16
of the NAND cell are commonly arranged as control gate lines CG
1
, CG
2
, CG
3
, . . . CG
8
. The control gate lines are used as word lines. The selection gates
14
9
,
16
9
and
14
10
,
16
10
are also continuously arranged in a row direction as selection gate lines SG
1
, SG
2
.
FIG. 3
shows an equivalent circuit of a memory cell array obtained by arranging NAND cells having the same configuration as the NAND cell described above in a matrix form. The source lines are connected to one reference potential (Vs) wiring formed of Al, polysilicon or the like for every 64 bit lines via a contact hole, for example. The reference potential wiring is connected to peripheral circuits. The control gates and first, second selection gates of the memory cell are continuously arranged in the row direction. Generally, a set of memory cells connected to the control gate is called one page and a set of pages disposed between the drain-side (first selection gate) and source-side (second selection gate) selection gates of one set is called one NAND block or simply one block. For example, one page is constructed by memory cells of 256 bytes (256×8). The memory cells of one page are substantially simultaneously programmed. For example, one block is constructed by memory cells of 2048 bytes (2048×8). The memory cells of one block are substantially simultaneously erased.
FIG. 4
shows the threshold voltage distribution of the NAND cell in which “0” indicates a programmed state and “1” indicates an erased state.
With the above construction, the data readout operation is effected by setting the bit line to an electrically floating state after precharging the bit line to Vcc, setting the control gate of a selected memory cell to 0V, setting the control gates and selection gates of the other memory cells to a power supply voltage Vread (for example, 3.5V), setting the source line to 0V, and detecting a variation in the bit line potential to check whether or not a current flows into the selected memory cell. That is, if data programmed in the memory cell is “0” (the threshold voltage of the memory cell Vth>0), the memory cell is set into the OFF state, and therefore, the bit line is kept at the precharged potential. On the other hand, if data programmed in the memory cell is “1” (the threshold voltage of the memory cell Vth<0), the memory cell is set into the ON state so as to cause the bit line potential to be lowered from the precharged potential by &Dgr;V. Data of the memory cell can be read out by detecting the bit line potential by use of a sense amplifier.
Further, in the data programming operation, 0V (“0” programming) or the power supply voltage Vcc (“1” programming) is applied to the bit line according to data to be programmed. The selection gate connected to the bit line is set to Vcc and the selection gate connected to the source line is set to 0V. At this time, 0V is transmitted to the channel of the cell in which “1” is programmed. At the time of “1” programming, since the selection gate connected to the bit line is turned OFF, the channel of the memory cell in which “1” is programmed is set to (Vcc-Vthsg (Vthsg is a threshold voltage of the selection gate)) and set into the electrically floating state. If the threshold voltage of the memory cell disposed nearer to the bit line side with respect to the memory cell in which data is to be programmed has a positive voltage Vthcell, the channel of the memory cell is set to (Vcc-Vthcell). After this, a boosted programming potential Vpgm (=approx. 20V) is applied to the control gate of the selected memory cell and an intermediate potential Vpass (=approx. 10V) is applied to the control gates of the non-selected memory cells. As a result, at the time of data “0”, since the channel potential is set at 0V, a high voltage is applied between the floating gate and the substrate of the selected memory cell so as to cause electrons to be injected from the substrate into the floating gate by the tunneling effect and shift the threshold voltage in a positive direction. On the other hand, at the time of data “1”, the channel set in the electrically floating state is set to an intermediate potential by the capacitive coupling with the control gate and no electrons are injected.
In the programming operation of the conventional NAND type flash memory, a verify read operation for checking whether or not the programming operation is sufficiently effected is effected after a programming pulse is applied. The re-programming operation is effected only for the memory cell in which the programming operation is detected to be insufficient by the verify read operation. The verify read operation is the same as the read operation described above except that the selected control gate is not set to 0V but is set to a potential Vvry (for example,
Takeuchi Ken
Tanaka Tomoharu
Banner & Witcoff , Ltd.
Cunningham Terry D.
Kabushiki Kaisha Toshiba
Tra Quan
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