Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-09-02
2002-11-19
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S390000
Reexamination Certificate
active
06483376
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of voltage generation circuits of the charge pump type. It applies in the field of circuits supplied by a voltage and in which it is necessary to generate a voltage higher than their supply voltage.
2. Discussion of the Related Art
Charge pump type circuits are typically used to supply capacitive type circuits, such as transistor gates. An application for these circuits is the provision of control potentials of power transistors used as switches. Another application is the provision of programming potentials to floating gate transistors, in electrically programmable memories.
FIG. 1
illustrates an example of a charge pump type generation circuit according to the state of the art. It supplies, on an output OP, a capacitive load represented by a capacitor Ceq. One pole of capacitor Ceq is connected to output OP and its other pole receives a reference potential Vss. The voltage across the capacitor is referred to as Vc.
An oscillator OSC, supplied by reference potential Vss and by a supply potential Vcc, provides a clock signal CK, illustrated in
FIG. 2
a
. Signal CK is a logic signal, the potential of which oscillates between Vcc, in the high state, and Vss, in the low state. Signal CK is issued to the first pole of a capacitor C
1
, and to the input of a logic inverter G
1
. Capacitor C
1
receives a precharge potential Vp on its second pole, via a diode D
1
. Potential Vp can be, for example, equal to potential Vcc. The anode of diode D
1
receives potential Vp and its cathode is connected to the second pole of capacitor C
1
.
Inverter G
1
generates a logic signal NCK, illustrated in
FIG. 2
b
, by inverting signal CK. Signal NCK is provided to the first pole of a capacitor C
2
. The second pole of capacitor C
2
is connected, on the one hand, to the cathode of a diode D
2
and to the anode of a diode D
3
. The anode of diode D
2
and the cathode of diode D
3
are connected, respectively, to the second pole of capacitor C
1
and to output OP.
It will be assumed that diodes D
1
, D
2
, and D
3
induce an identical voltage drop Vd when they are forwardly conductive, and that Vcc>Vd and Vp>Vd. Assume that signal Ck is in the low state. Capacitor C
1
receives potential Vss on its first pole and a potential Vp−Vd on its second pole. When signal CK switches to the high state, the potential of the second pole of capacitor C
1
switches to value (Vp−Vd)+Vcc. A charge transfer to the second pole of capacitor C
2
will then be performed, through diode D
2
. Diode D
1
is then blocked and prevents the discharge of capacitor C
1
to the node providing potential Vp. The potential of the second pole of capacitor C
2
switches to value Vp+Vcc−2*Vd. The potential of the first pole of capacitor C
2
is then equal to Vss. When signal CK switches back to the low state, diode D
2
is blocked (non-conducting) and the potential of the second pole of capacitor C
2
is increased. This potential then switches to (Vp+Vcc−2*Vd)+Vcc. By charge transfer through diode D
3
, voltage Vc will be progressively brought to value (Vp+2*Vcc)−3*Vd (assuming that Vss=0 volt). By using n stages, two successive stages respectively receiving signals CK and NCK, the potential generated by the voltage generation circuit can thus be brought to (Vp−Vd)+n*(Vcc−Vd).
An important feature of charge pump type circuits is the delay required for the output potential to reach the desired value. It is generally attempted to obtain very short delays (also called rise times). In practice, the rise time can be shown to be inversely proportional to the value of the capacitors used. The use of capacitors of high values indeed enables transfer, in each cycle, of a greater number of charges to the output, which decreases the rise time. However, the increase of the capacitor values can raise a problem of implementation and/or of bulk, in integrated circuits.
SUMMARY OF THE INVENTION
An aim of the present invention is to provide an improved circuit which, for an equal rise time, decreases the capacitor values.
For this purpose, it is provided to generate the control signals via a self-oscillating control circuit. Time phases during which the potentials of the control signals are stable are thus eliminated, these time phases corresponding to the end of charge and discharge phases of the capacitors of the voltage generation circuit.
Thus, the present invention provides a potential generation circuit of charge pump type, this circuit including at least two stages formed of capacitors and of means for isolating or interconnecting the capacitors, to generate an output potential by charge transfer between the stages. The circuit is driven by at least two control potentials, the capacitors receiving one of the control potentials on a first pole. The two control potentials oscillate between a first and a second value so that they control, on the one hand, a charge phase of the capacitors when they switch from the first value to the second value and, on the other hand, a discharge phase of the capacitors when they switch from the second value to the first value. The circuit includes a self-oscillating control circuit to generate, on outputs, the control potentials, the control circuit receiving the control potentials on inputs and being arranged so that these control potentials be modified as soon as they reach the first or the second value.
According to an embodiment, the control circuit includes a comparator for comparing the control potentials with a reference potential to modify the values of the control potentials according to the result of the comparison.
According to an embodiment, the reference potential corresponds to the first value of the control potentials.
According to an embodiment, the control circuit includes an RS flip-flop at the output of the comparator, to guarantee that the control potentials do not overlap.
According to an embodiment, the comparator receives the control potentials on inverting inputs and the flip-flop is of NAND type.
According to an embodiment, the control potentials are generated by buffer circuits driven by outputs of the flip-flop.
According to an embodiment, the control potentials are generated by buffer circuits driven by outputs of the comparator.
According to an embodiment, the buffer circuits are inverters.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 5097226 (1992-03-01), Pascucci et al.
patent: 5483434 (1996-01-01), Seesink
patent: 5677645 (1997-10-01), Merritt
patent: 5818289 (1998-10-01), Chevallier et al.
patent: A-2 692 415 (1993-12-01), None
Bienvenu Philippe
Pavlin Antoine
Cunningham Terry D.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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