Voltage generating circuit

Details Voltage generating circuit Voltage generating circuit

1997-08-04

1999-06-22

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327237, 327243, G05F 110

Patent

active

059146311

ABSTRACT:
A voltage controlled delay circuit is formed by m number of gates connected in series, phases of a clock signal and a delay signal are compared by a phase comparator, an up signal or a down signal is output, an integrated signal is generated by an integrator, a voltage signal following this is generated by a buffer and fed back as an operating power source voltage to the voltage controlled delay circuit, and further an internal power source voltage following the voltage signal is generated by a buffer and a pMOS transistor, therefore the internal power source voltage of the required lowest limit can be supplied in response to the frequency of the clock and a reduction of the voltage and conservation of the electric power of the LSI circuit can be achieved.

REFERENCES:
patent: 4902920 (1990-02-01), Wolaver
patent: 5382921 (1995-01-01), Estrada et al.
patent: 5642082 (1997-06-01), Jefferson
patent: 5670903 (1997-09-01), Mizuno
patent: 5742195 (1998-04-01), Mizuno et al.
patent: 5757238 (1998-05-01), Ferraiolo et al.

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