Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-01-06
2001-08-28
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C345S089000, C341S144000
Reexamination Certificate
active
06281826
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage generating apparatus, and more particularly to a D/A converter, a method of designing a D/A converter, a method of precharging signal lines, a circuit for precharging signal lines, and a liquid crystal panel substrate and liquid crystal display device using the above component(s) and method(s).
2. Background of the Invention
A great number of techniques have been developed to generate a voltage in response to a given signal. However, the problems of these known techniques are that the voltage can deviate from a desired value and that a long time is required for the voltage to reach the final desired value. These problems will be discussed in further detail below.
(1) Deviation of Voltage
One known technique of constructing a D/A converter is to use capacitors. The advantage of the D/A converter using capacitors over the D/A converter with resistors is its low power consumption. One type of the D/A converter using capacitors is one with capacitors having capacitance values weighted in a binary fashion.
FIG. 74
is a circuit diagram illustrating a conventional D/A converter with binary-weighted capacitors.
This D/A converter shown in
FIG. 74
generates an analog output signal corresponding to a 6-bit digital input signal. More specifically, a 6-bit digital signal representing a binary number in the range from “000000” to “111111” (from “0” to “63” in decimal) is input wherein the 6 bits D
11
-D
16
corresponding to the first to sixth digits of the binary number respectively are input via six digital signal lines
5001
.
The respective bits D
11
-D
16
of the input digital signal are stored in 2-stage latches A
11
-A
16
and B
11
-B
16
. The latches A
11
-A
16
and B
11
-B
16
operate in response to clock signals CL
1
and CL
2
and also to inverted clock signals nCL
1
and nCL
2
. These clock signals CL
1
and CL
2
and inverted clock signals nCL
1
and nCL
2
are generated from the output signal of a shift register (not shown).
The D/A converter has an interconnection line
5002
(at a voltage Vo), interconnection line
5003
(at a voltage Vs), interconnection line
5004
(at ground voltage GND), wherein Vo>Vs>GND. The D/A converter also has an interconnection line
5005
for outputting the analog output signal.
One electrode of each conversion capacitor C
11
-C
16
is connected to the interconnection line
5002
. The conversion capacitors C
11
-C
16
are designed to have binary-weighted capacitance values. That is, the ratios of the capacitance values are given by:
C
11
: C
12
: C
13
: C
14
: C
15
: C
16
=1: 2: 4: 8: 16: 32.
The operation of this D/A converter is described below for the specific case where a digital signal of “000001” is input. In this case, the bit D
11
of the input signal is “H” (high), and thus an “H”-level signal is held by the latch A
11
. On the other hand, the bits D
12
-D
16
of the digital input signal are “L” (low), and therefore the latches A
12
-A
16
hold an “L”-level signal. When a latch pulse is input, the signals held by the 1st-stage latches A
11
-A
16
are transferred to the 2nd-stage latches B
11
-B
16
in response to the clock signal CL
2
and the inverted clock signal nCL
2
.
Then the reset signal R on the interconnection line
5006
is raised to “H” thereby turning on analog switches Ta
1
-Ta
6
. As a result, the voltage across each conversion capacitor C
11
-C
16
becomes zero, and thus the charge stored in these capacitors goes out. At the same time, an analog switch T
3
is turned on so that a charge corresponding to the difference between the voltage of the interconnection line
5003
(Vs) and the voltage of the interconnection line
5004
(GND) is stored in a reference capacitor Cs
1
. As a result, the reference capacitor Cs
1
has a charge Qs given by
Qs=Cs
1
·Vs
(1—1)
Then the reset signal R falls down to “L”, and the analog switches Ta
1
-Ta
6
turn off. Furthermore, the set signal S on the interconnection line
5007
is raised to “H”. AND operation is performed between the H level of the set signal S and the output level of the respective latches B
11
-B
16
. Analog switches Tb
1
-Tb
6
are turned on or off depending on the corresponding results of the AND operation.
In this specific example, the analog switch Tb
1
corresponding to the latch B
11
is turned on, and, as a result, the conversion capacitor C
11
is connected to the reference capacitor Cs
1
via the analog switch Tb
1
. A part of the charge Qs stored in the reference capacitor Cs
1
moves into the conversion capacitor C
11
.
On the other hand, the analog switches Tb
2
-Tb
6
corresponding to the latches B
12
-B
16
are in off-states, and the conversion capacitors C
12
-C
16
are not connected to the reference capacitor Cs
1
.
As a result of the above operation, the output voltage Vout on the interconnection line
5005
becomes as follows. The charge Qs stored in the reference capacitor Cs
1
partially moves into the conversion capacitor C
11
. After the movement of the charge, the reference capacitor Cs
1
has a charge Qs' and the conversion capacitor C
11
has a charge Q
11
′ wherein Qs' and Q
11
′ are given by
Qs′=Cs
1
·Vout
(1-2)
Q
11′=
C
11·(
Vout−Vo
) (1-3)
Here, Qs=Qs′+Q
11
′, thus from equations (1—1) through (1-3), the following equation is obtained.
Cs
1−
Vs=Cs
1·
Vout+C
11·(
Vout—Vo
)
From the above equation, Vout is given as
Vout=
(
Cs
1·
Vs+C
11·
Vo
)/(
Cs
1+
C
11)
The above result has been obtained on the assumption that a digital input signal of “000001” is given. If the above discussion is expanded for general digital input signals, then the Vout becomes
Vout=
(
Cs
1·
Vs+V
11&Sgr;
DiCi
)/(
Cs
1+&Sgr;
DiCi
) (1-4)
where the summation &Sgr; is performed for i=11, 12, 13, 14, 15, and 16, and Di has a value of 1 when the corresponding bits of D
11
-D
16
of the digital signal is at an “H” level while Di has a value of 0 when the corresponding bits of D
11
-D
16
of the digital signal is at an “L” level.
FIG. 75
illustrates the typical conversion characteristic of the conventional D/A converter described above. As can be seen, the analog output signal is a function of the digital input signal wherein the analog output signal varies along a gradually curved line. In other words, the conversion characteristic of the conventional D/A converter is not linear.
The reason for the nonlinearity is that the denominator of equation (1-4) has a term (&Sgr;DiCi) which varies depending on the values of the bits D
11
-D
16
of the digital input signal, and the variation in this term causes a deviation from the proportional relationship. To avoid the above problem, it is required that the denominator should be a constant.
Furthermore, the conventional D/A converter has discontinuities in its conversion characteristic, which can cause a deviation from a desired output voltage. In
FIG. 75
, for example, there is a discontinuous reverse change at a point where the digital input signal has a value of “32” in decimal (100000 in binary). That is, the analog output voltage for the input of “32” becomes lower than the output voltage for the input of “31” (011111 in binary). The above discontinuity occurs if the ratio of the conversion capacitance C
16
corresponding to the most significant bit to the sum of the conversion capacitances C
11
-C
15
corresponding to the less significant bits has a deviation from an ideal ratio 32:31.
In practice, it is difficult to produce capacitors without introducing any deviation from the ideal values. In particular, in the case of a large capacitance, there is a tendency that the error from the designed value becomes large. For the above reason, the analog output voltage can deviate from the ideal value corresponding to the digital input signal, and the analog output voltage can even decrease with the increase in the digital input signal
Nguyen John B
Oliff & Berridg,e PLC
Seiko Epson Corporation
Young Brian
LandOfFree
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