Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Patent
1997-10-07
1999-05-11
Young, Brian
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
H03M1/66
Patent
active
059032340
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a voltage generating apparatus, and more particularly to a D/A converter, a method of designing a D/A converter, a method of precharging signal lines, a circuit for precharging signal lines, and a liquid crystal panel substrate and liquid crystal display device using the above component(s) and method(s).
BACKGROUND OF THE INVENTION
A great number of techniques have been developed to generate a voltage in response to a given signal. However, the problems of these known techniques are that the voltage can deviate from a desired value and that a long time is required for the voltage to reach the final desired value. These problems will be discussed in further detail below.
One known technique of constructing a D/A converter is to use capacitors. The advantage of the D/A converter using capacitors over the D/A converter with resistors is its low power consumption. One type of the D/A converter using capacitors is one with capacitors having capacitance values weighted in a binary fashion. FIG. 74 is a circuit diagram illustrating a conventional D/A converter with binary-weighted capacitors.
This D/A converter shown in FIG. 74 generates an analog output signal corresponding to a 6-bit digital input signal. More specifically, a 6-bit digital signal representing a binary number in the range from "000000" to "111111" (from "0" to "63" in decimal) is input wherein the 6 bits D11-D16 corresponding to the first to sixth digits of the binary number respectively are input via six digital signal lines 5001.
The respective bits D11-D16 of the input digital signal are stored in 2-stage latches A11-A16 and B11-B16. The latches A11-A16 and B11-B16 operate in response to clock signals CL1 and CL2 and also to inverted clock signals nCL1 and nCL2. These clock signals CL1 and CL2 and inverted clock signals nCL1 and nCL2 are generated from the output signal of a shift register (not shown).
The D/A converter has an interconnection line 5002 (at a voltage Vo), interconnection line 5003 (at a voltage Vs), interconnection line 5004 (at ground voltage GND), wherein Vo>Vs>GND. The D/A converter also has an interconnection line 5005 for outputting the analog output signal.
One electrode of each conversion capacitor C11-C16 is connected to the interconnection line 5002. The conversion capacitors C11-C16 are designed to have binary-weighted capacitance values. That is, the ratios of the capacitance values are given by:
The operation of this D/A converter is described below for the specific case where a digital signal of "000001" is input. In this case, the bit D11 of the input signal is "H" (high), and thus an "H"-level signal is held by the latch A11. On the other hand, the bits D12-D16 of the digital input signal are "L" (low), and therefore the latches A12-A16 hold an "L"-level signal. When a latch pulse is input, the signals held by the 1st-stage latches A11-A16 are transferred to the 2nd-stage latches B11-B16 in response to the clock signal CL2 and the inverted clock signal nCL2.
Then the reset signal R on the interconnection line 5006 is raised to "H" thereby turning on analog switches Ta1-Ta6. As a result, the voltage across each conversion capacitor C11-C16 becomes zero, and thus the charge stored in these capacitors goes out. At the same time, an analog switch T3 is turned on so that a charge corresponding to the difference between the voltage of the interconnection line 5003 (Vs) and the voltage of the interconnection line 5004 (GND) is stored in a reference capacitor Cs1. As a result, the reference capacitor Cs1 has a charge Qs given by
Then the reset signal R falls down to "L", and the analog switches Ta1-Ta6 turn off. Furthermore, the set signal S on the interconnection line 5007 is raised to "H". AND operation is performed between the H level of the set signal S and the output level of the respective latches B11-B16. Analog switches Tb1-Tb6 are turned on or off depending on the corresponding results of the AND operation.
In this
REFERENCES:
patent: 4937578 (1990-06-01), Shioda
patent: 5453757 (1995-09-01), Date et al.
Seiko Epson Corporation
Young Brian
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