Static information storage and retrieval – Powering
Reexamination Certificate
2001-01-05
2002-01-08
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Powering
C365S189110
Reexamination Certificate
active
06337827
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage dropping power unit adapted to drop an internal supply voltage of semiconductor memory device-mounted information processing equipment such as a personal computer and to supply a predetermined operating voltage obtained by dropping the internal supply voltage to a semiconductor memory device such as a RAM (Random Access Memory) or a like mounted on the information processing equipment and more particularly to the voltage dropping power unit capable of reducing power consumption in the voltage dropping power unit itself while the semiconductor memory device is placed in a quiescent state.
2. Description of the Related Art
Generally, in a section on which a semiconductor memory device is packaged is embedded a voltage dropping power unit used to supply an operating voltage obtained by dropping an internal supply voltage of semiconductor memory device-based information processing equipment to a semiconductor memory device. That is, the internal supply voltage is dropped by the voltage dropping power unit and a dropped voltage is applied as the operating voltage to the semiconductor memory device including a memory array or a like.
As shown in
FIG. 6
, a conventional voltage-dropping power unit
1
is provided with a voltage control circuit
2
having an active element
5
adapted to generate, using a supply voltage Vcc, a dropped voltage Vdd obtained by being controlled depending on a control voltage, a reference circuit
3
composed of an active element for calibrating currents
6
and voltage-dividing resistors
7
a
and
7
b
making up a group of voltage-dividing resistors and adapted to produce a predetermined reference voltage to be set by the active element
6
and a differential circuit
4
adapted to receive the reference voltage from the reference circuit
3
as an input voltage and an output voltage from the voltage control circuit
2
as an input voltage and to feed the control voltage to the voltage control circuit
2
so that both the input voltages are made equal. The reference circuit
3
outputs a voltage which has dropped at a node A when currents have flowed through the group of the voltage-dividing resistors, as the reference voltage, to the differential circuit
4
. The differential circuit
4
is a so-called current mirror amplifying circuit which is provided with a current path composed of an active element
8
a
to receive a supply voltage Vcc and of an active element
9
a
connected in serial to the active element
8
a
to receive the dropped voltage Vdd being fed back from the voltage control circuit
2
and with a current path composed of an active element
8
b
to connect to a terminal of a supply voltage Vcc and of an active element
9
b
connected in serial to the active element
8
b
to receive the reference voltage and adapted to take out the control voltage based on a potential at a node B connected between the active element
8
b
and the active element
9
b
. Currents flowing through both the current paths can be adjusted by an active element for adjusting sensitivity
10
. A voltage taken out from a node C between the active element
9
a
and the active element
8
a
is fed to the active element
9
a
and to the active element
9
b
to be used as the control voltage.
The differential circuit
4
performs a differential operation so that currents flowing through both the current paths are made equal and therefore the output voltage from the voltage control circuit
2
is made equal to the reference voltage, thus enabling the output voltage from the voltage control circuit
2
, that is, the dropped voltage Vdd to be held at a constant value.
However, while the semiconductor memory device is placed in a quiescent state, the conventional voltage-dropping power unit continues to operate even when the semiconductor memory device is placed in operation. That is, in
FIG. 6
, in the reference circuit
3
, constant currents flow, irrespective of whether the semiconductor memory device is in operation or in quiescent operation, through the active element for calibrating current
6
and the group of the voltage dividing resistors and the reference circuit
3
continues to output the predetermined reference voltage to the differential circuit
4
. Moreover, in the differential circuit
4
which receives the reference voltage, currents continue to flow through the current path composed of the active elements
8
a
and
9
a
and through the current path composed of the active elements
8
b
and
9
b
and then through the active element
10
for adjusting sensitivity. As a result, even when the semiconductor memory device is in a quiescent state, power is consumed in the voltage dropping power unit in the same manner as in the case of in the semiconductor memory device being in operation.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a voltage dropping power unit being capable of reducing power consumption in the voltage dropping power unit while a semiconductor memory device is placed in a quiescent state.
According to a first aspect of the present invention, there is provided a voltage dropping power unit for dropping a supply voltage and for applying a dropped voltage to a semiconductor memory device, including:
a voltage control circuit to produce a voltage to be controlled depending on a control voltage in order to supply an operating voltage to the semiconductor memory device;
a reference voltage generating circuit to generate a reference voltage used to produce the control voltage;
a voltage differential circuit to perform a differential operation so that the voltage output from the voltage control circuit is made equal to the reference voltage irrespective of a level of said voltage output from the voltage control circuit; and
wherein the reference voltage generating circuit is provided with a voltage dividing resistor to generate the reference voltage by receiving a current from a supply voltage source and a switching device to form a short-circuit across the voltage dividing resistor in order to decrease an operating current flowing through the voltage differential circuit while the semiconductor memory device is placed in a quiescent state.
In the foregoing, a preferable mode is one wherein the switching device in the reference voltage generating circuit is provided with a transistor device operated to form the short-circuit when the semiconductor memory device is in quiescent operation.
Also, a preferable mode is one wherein the reference voltage generating circuit includes an active device connected in serial to the voltage dividing resistor to adjust an amount of a current flowing through the voltage dividing resistor for making the reference voltage adjustable.
Also, a preferable mode is one wherein the transistor device is an n-type MOS (Metal Oxide Semiconductor) transistor used to receive a signal informing a quiescent operation of the semiconductor memory device.
Also, a preferable mode is one wherein the signal informing a quiescent operation of the semiconductor memory device is a negative logical signal and wherein the n-type MOS transistor receives the signal as an inverted signal through an inverter.
Also, a preferable mode is one wherein the MOS transistor and the voltage dividing resistor are connected in parallel and wherein the voltage dividing resistor is short-circuited when the inverted signal is fed to the MOS transistor.
Also, a preferable mode is one wherein the differential circuit is provided with a pair of MOS transistors being connected in parallel with each other and each having a gate and wherein the gate of one of said MOS transistors acts as an input terminal to receive a reference voltage from the reference voltage generating circuit and the gate of the other of the MOS transistors acts as an input terminal to receive an output voltage from the voltage control circuit.
Also, a preferable mode is one wherein the one MOS transistor making up the pair of MOS transistors i
Mitoma Tetsuya
Nakatake Yoshihiro
Nguyen Tan T.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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