Voltage drop circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S543000

Reexamination Certificate

active

06281744

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a voltage drop circuit for a semiconductor memory device.
2. Description of the Background Art
FIG. 1
is a circuit view illustrating a conventional voltage drop circuit which generates a stable internal voltage Vint. As shown therein, the conventional voltage drop circuit includes a comparator
10
, a current supply unit
12
and a load circuit
14
.
The comparator
10
includes a current mirror type amplifier and compares voltage levels of predetermined reference voltage Vref and internal voltage Vint using a negative feedback loop. The current supply unit
12
includes a PMOS transistor M
1
connected between an external voltage Vext and an output terminal
50
thereof and it is activated in accordance with a comparison signal N
1
of the comparator
10
. The load circuit
14
is connected between the output terminal
50
and ground voltage Vss, thereby forming the internal voltage Vint in accordance with the current I
1
from the current supply unit
12
.
The operation of the conventional voltage drop circuit will now be explained.
If the internal voltage Vint is less than the predetermined reference voltage Vref, the comparator
10
outputs the comparison signal N
1
at low level and turns on the PMOS transistor M
1
of the current supply unit
12
. As a result, the predetermined current I
1
from the current supply unit
12
flows toward the load circuit
14
so as to form a predetermined level of interval voltage Vint.
When the internal voltage Vint is increased and accordingly the reference voltage Vref is increased, the comparator
10
outputs the comparison signal N
1
at high level and turns on the PMOS transistor M
1
of the current supply unit
12
, whereby the current supply from the current supply unit
12
to the load circuit
14
is interrupted.
Therefore, the conventional voltage drop circuit repeatedly implements the above operation so as to maintain the internal voltage Vint at a constant level.
Presently, as memory capacity becomes highly integrated and miniaturized, an external voltage Vext is decreased to a low voltage (for example, 3.3V→2.5V). Here, when the external voltage Vext is decreased to a low voltage, a voltage Vds between source and drain of the PMOS transistor M
1
of the current supply unit
12
, thereby deteriorating a current supply capability of the current supply unit
12
. As a result, when the load circuit
14
is driven, the internal voltage Vint may be disadvantageously unstable.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming the disadvantages of the conventional voltage drop circuit.
Accordingly, it is an object of the present invention to provide a voltage drop circuit, capable of generating a stable internal voltage by improving a current driving capability of a current supply unit when an external voltage is decreased to a low voltage.
To achieve the above-described object, there is provided a voltage drop circuit according to the present invention which includes a comparator for comparing a predetermined reference voltage and a generated internal voltage, a first current supply unit for being activated in accordance with an output of the comparator, a level converter for converting the output of the comparator to a CMOS level, a second current supply unit for being activated in accordance with an output of the level converter, and a load circuit for receiving current from the first and second current supply units and forming an internal voltage.
The features and advantages of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific example, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 5485117 (1996-01-01), Furumochi
patent: 5493234 (1996-02-01), Oh
patent: 5504452 (1996-04-01), Takenaka
patent: 5557193 (1996-09-01), Kajimoto
patent: 5612920 (1997-03-01), Tomishima

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