Voltage droop mitigation through instruction issue throttling

Details Voltage droop mitigation through instruction issue throttling Voltage droop mitigation through instruction issue throttling

2011-05-03

2011-05-03

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S215000, C713S300000, C713S320000, C713S323000

Reexamination Certificate

active

07937563

ABSTRACT:
A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events. Instruction issue throttling occurs if either a difference between the old activity average and the recent activity average exceed a first threshold or the recent activity average exceeds a second threshold.

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