Voltage downconverter circuit capable of reducing current...

Details Voltage downconverter circuit capable of reducing current... Voltage downconverter circuit capable of reducing current...

2001-01-19

2003-02-04

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S316000, C327S538000, C365S227000

Reexamination Certificate

active

06515461

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a voltage downconverter circuit provided in a semiconductor integrated circuit device. In particular, the invention relates to a structure of a voltage downconverter circuit provided in a semiconductor memory device.
2. Description of the Background Art
Semiconductor integrated circuits generally include therein a voltage downconverter circuit (hereinafter referred to as VDC circuit) receiving an external supply voltage ext.Vcc and lowering the voltage to generate an internal supply voltage Int.Vcc for the purpose of reducing power consumption of the circuits.
FIG. 12
is a circuit diagram showing a structure of such a conventional VDC circuit
2000
.
Referring to
FIG. 12
, the conventional VDC circuit
2000
includes a differential amplifier
2100
receiving a reference potential Vref supplied from a reference potential generating circuit (not shown) and a potential on a node nv from which an internal supply potential Int.Vcc is output to provide from a node COMP a result of comparison therebetween, and a P channel driver transistor P
1
provided between an external supply potential ext.Vcc and node nv and controlled by the output signal from output node COMP of differential amplifier
2100
to maintain the potential level on node nv equal to reference potential Vref.
Differential amplifier
2100
includes a P channel MOS transistor P
11
and an N channel MOS transistor N
11
provided in series between external supply potential ext.Vcc and a common node nc, and a P channel MOS transistor P
12
and an N channel MOS transistor N
12
provided between external supply potential ext.Vcc and common node nc. Between common node nc and a ground potential GND, an N channel MOS transistor N
1
is provided having its gate receiving a control signal ACT.
Respective gates of transistors P
11
and P
12
are connected to each other and the gate and drain of transistor P
12
are connected. The gate of transistor N
11
receives reference potential Vref and the gate of transistor N
12
is connected to node nv.
The connection node between transistors P
11
and N
11
corresponds to output node COMP of differential amplifier
2100
.
Specifically, in this structure, differential amplifier
2100
receives, when signal ACT is in the active state (“H” level: the level of external supply potential ext.Vcc) and differential amplifier
2100
is in the active state, reference potential Vref and internal supply potential Int.Vcc as inputs and compares these potentials to accordingly lower a voltage on node COMP if internal supply potential Int.Vcc is lower than reference potential Vref Consequently, driver transistor P
1
is activated and control is made to set the potential level on node nv equal to reference potential Vref.
VDC circuit
2000
further includes a P channel MOS transistor P
2
provided between external supply potential ext.Vcc and the gate of transistor P
1
and receiving signal ACT at its gate.
Transistor P
2
prevents internal supply potential Int.Vcc from rising when differential amplifier
2100
is inactive (when signal ACT is at “L” level). In other words, if transistor P
2
is not provided and differential amplifier
2100
is inactive, a slight amount of current continues flowing to node nv via transistor P
1
because the potential on node COMP does not rise to the level of external supply potential ext.Vcc. Consequently, increase of internal supply potential Int.Vcc occurs.
In order to accomplish a stable operation of differential amplifier
2100
, a constant current source is required. In the conventional VDC circuit
2000
, transistor N
1
(hereinafter referred to as constant current source transistor N
1
) operates as the constant current source. Specifically, transistor N
1
is structured to operate as the constant current source for differential amplifier
2100
when it receives signal ACT of the activation level (H level). The activation level of ACT signal for activating the VDC circuit is the level of external supply potential ext.Vcc.
From the opposite point of view, in the active period of a semiconductor integrated circuit device, for example, a semiconductor memory device provided with such a VDC circuit
2000
, there is a problem of increase of power consumption since a through current constantly flows through VDC circuit
2000
even if any internal circuit consumes no current (this state is referred to as active standby state).
Further, when the external supply voltage varies (generally a variation of ±10% is compensated according to an operational specification), the amount of current flowing through constant current source transistor N
1
in differential amplifier
2100
shown in
FIG. 12
changes depending greatly on the external supply voltage. If the external supply voltage becomes lower, the amount of current flowing through transistor N
1
decreases. This decrease lowers the speed of reducing the voltage on node COMP of differential amplifier
2100
, resulting in a problem of deterioration in responsiveness of VDC circuit
2000
.
It could be possible to define the drive current of transistor N
1
in order to secure a sufficient amount of current even when the external supply voltage is low and thus prevent the responsiveness of the circuit from deteriorating in the event of such a variation in the external supply voltage. However, in this case, if the external supply voltage is high, the amount of current flowing through transistor N
1
accordingly increases, resulting in a problem of an excessive through current.
In order to address this problem, Japanese Patent Laying-Open No. 11-3586 discloses a structure of a VDC circuit capable of reducing such a through current as discussed above.
FIG. 13
is a circuit diagram showing the structure of the conventional VDC circuit
3000
disclosed in Japanese Patent Laying-Open No. 11-3586.
VDC circuit
3000
and VDC circuit
2000
shown in
FIG. 12
are different in structure as described below.
VDC circuit
3000
includes a differential amplifier
2200
instead of differential amplifier
2100
. In differential amplifier
2200
, the gate potential of a constant current source transistor N
1
is controlled by a reference potential Vref instead of signal ACT controlling the gate potential of constant current source transistor N
1
of differential amplifier
2100
. In addition, differential amplifier
2200
includes an N channel MOS transistor N
2
provided between a common node nc and constant current source transistor N
1
to receive a signal ACT at its gate.
The structure as shown in
FIG. 13
of VDC circuit
3000
allows the gate potential of constant current source transistor N
1
to be controlled by reference potential Vref. Therefore, variation of a through current can be prevented even when the external supply voltage varies.
It should be noted here that a reference potential generating circuit (not shown) for generating reference potential Vref may be defined to operate with a limited low amount of current for the purpose of preventing increase in power consumption since the reference potential generating circuit operates all the time. In this case, if the gate of transistor N
1
is connected to the output of reference potential generating circuit as shown in
FIG. 13
, the reference potential generating circuit has its output connected to an increased load capacitance. As a result, rise of the reference potential after power is applied could be delayed.
In general, a node from which the reference potential is applied is of high impedance. If such a node is frequently used, noise could appear on a line for supplying the reference potential.
Further, when an increased amount of current is consumed that is supplied by internal supply potential Int.Vcc, voltage drop occurs on internal supply potential Int.Vcc. This results in reduction of a potential on an output node COMP of differential amplifier
2200
shown in FIG.
13
. At this time, due to a coupling effect by a transistor N
11
, reduction of reference pot

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