Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-05-30
2001-09-11
Han, Jessica (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C323S280000, C323S281000, C323S314000
Reexamination Certificate
active
06288526
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to voltage conversion circuits, and more particularly, to a voltage regulator circuit in an integrated circuit device.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) devices typically include numerous transistors that are fabricated on, for example, silicon wafers. To increase production yields and lower total IC device costs, semiconductor manufacturers are continually striving to reduce the size of the transistors in IC devices. However, for a given power supply voltage, the electric field strength, e.g., the change in voltage per unit length, that these transistors are exposed to increases as the size of the transistors is reduced. As IC device geometries shrink to the deep sub-micron level (i.e. less than 0.5 um), the electric fields generated by the 5V supply voltages historically used to power IC devices can degrade or even destroy the transistors in those IC devices. For example, the performance of a sub-micron MOS transistor having an effective channel length of 0.35 um is impaired under a 5V supply voltage due to injection of hot electrons into the gate of the MOS transistor. In addition, the electric field generated by a 5V supply voltage across a sub-micron MOS transistor can also cause total failure due to gate oxide breakdown. Therefore, a reduced power supply voltage must be available to reap the cost and efficiency benefits of deep sub-micron transistors while maintaining overall IC performance and reliability. The recent trend towards the use of 3.3V supply voltages is indicative of this need, and further reductions in supply voltages will become necessary as IC device geometries continue to shrink.
At the same time, a 3.3V external supply voltage will not necessarily be available to power deep sub-micron IC devices. While memory and microprocessor boards can often be custom designed to provide 3.3V to those IC devices, other types of IC devices may not have that option available. For example, Programmable Logic Devices (PLD's) are a type of IC device comprising user-configurable logic elements and interconnect resources that are programmable to implement user-defined logic operations (that is, a user's circuit design). PLD's have begun to incorporate 0.35 um transistors that require the 3.3V power supply voltage. However, because of their configurable purpose, PLD's will often be used in systems that operate under 5V power supply voltages due to other IC devices in the system that require 5V, such as TTL or ECL devices. Therefore, many IC devices include a voltage down converter (VDC) to reduce an external power supply voltage to the level required by the transistors in those IC devices.
FIG. 1
a
shows a conventional VDC
100
used in the EPF10K50V PLD from ALTERA Corporation in San Jose, Calif. VDC
100
comprises NMOS transistors
101
,
102
, and
103
, and an adjustment circuit
105
. NMOS transistor
103
is coupled between an external power supply voltage terminal and an output terminal
104
. Adjustment circuit
105
is coupled between output terminal
104
and the gate terminal of NMOS transistor
103
. NMOS transistors
101
and
102
are both drain-gate coupled and are serially connected between the external power supply voltage terminal and the gate terminal of NMOS transistor
103
. As a result, an external supply voltage Vccext at the external power supply voltage terminal is reduced by the threshold voltage drops across NMOS transistors
101
and
102
, thereby applying a voltage Vg to the gate terminal of transistor
103
. Voltage Vg is given by the equation:
Vg=Vccext−Vtn(
101
)−Vtn(
102
) [1]
where Vtn(
101
) and Vtn(
102
) are the threshold voltage drops across NMOS transistors
101
and
102
, respectively. Voltage Vg brings NMOS transistor
103
into conduction, thereby providing a reference voltage Vccint at output terminal
104
. Reference voltage Vccint is given by the equation:
Vccint=Vg−Vtn(
103
) [2]
where Vtn(
103
) is the threshold voltage drop across NMOS transistor
103
. Therefore, reference voltage Vccint is effectively “programmed” by NMOS transistors
101
,
102
, and
103
. If the three NMOS transistors are matched, combining equations [1] and [2] yields:
Vccint=Vccext−3Vtn [3]
where Vtn is the threshold voltage drop across each of NMOS transistors
101
,
102
, and
103
. Because voltage vg is less than external supply voltage Vccext, NMOS transistor
103
cannot provide a voltage Vccint greater than voltage Vg at output terminal
104
. Therefore, NMOS transistors
101
and
102
effectively “program” reference voltage Vccint. For example, a typical value for the threshold voltage drop of an NMOS transistor is 0.5V. In that case, the reference voltage Vccint provided by VDC
100
for an external supply voltage Vccext of 5.0V would be 3.5V (i.e., 5.0V−3*(0.5V)=3.5 V), which would be suitable for driving 3.3V IC devices. Adjustment circuit
105
helps to maintain output stability under load variations. If the load current required from output terminal
104
increases, adjustment circuit
105
forces voltage Vg higher to drive more current through NMOS transistor
103
. On the other hand, if voltage Vccint rises excessively, adjustment circuit
105
decreases voltage Vg to compensate. However, although VDC
100
is a simple circuit for providing a reduced reference voltage, it is unacceptable for situations requiring a precise, stable reference voltage. First, any variations in the value of external supply voltage Vccext directly affect the value of reference voltage Vccint. In addition, the threshold voltage drop Vtn across transistors
101
and
102
varies with process, making a specific reference voltage Vccint difficult to achieve. Finally, the threshold voltage drop Vtn also varies with temperature, leading to fluctuations in reference voltage Vccint during normal operation of VDC
100
.
FIG. 1
b
shows a VDC
110
, as described by Ishibashi et al. in “A Voltage Down Converter with Submicroampere Standby Current for Low-Power Static RAM's” (
IEEE Journal of Solid-State Circuits
, Vol. 27, No. 6, June 1992.). VDC
110
provides a stable reference voltage of 4.5V to optimize power dissipation, reliability, and operation speed in a static random access memory (SRAM). VDC
110
comprises a depletion-mode NMOS transistor
112
, matched PMOS transistors
131
-
133
, matched NMOS transistors
141
-
145
, matched NMOS transistors
151
-
153
, and matched depletion-mode NMOS transistors
161
-
163
. Depletion-mode NMOS transistor
112
, PMOS transistor
131
, and NMOS transistor
141
are serially coupled between an external voltage supply terminal and ground. PMOS transistor
132
and NMOS transistor
142
are serially coupled between the external voltage supply terminal and ground. PMOS transistor
133
and depletion-mode transistors
151
-
153
are serially coupled between the external voltage supply terminal and ground. Finally, depletion-mode NMOS transistors
161
-
163
are serially coupled with NMOS transistors
143
-
145
, respectively, between the external voltage supply terminal and ground.
When a voltage Vccext is applied to the external Vcc supply terminal, gate-source coupled depletion-mode NMOS transistor
112
is forced to operate in its linear region and generates a small programming current Iprog. Because depletion-mode NMOS transistor
112
is operating in its linear region, programming current Iprog is relatively independent of supply voltage and temperature variations. Meanwhile, since the gate and drain terminals of PMOS transistor
132
are coupled to the gate terminal of PMOS transistor
131
, PMOS transistor
132
is biased into conduction and attempts to mirror the current flowing through PMOS transistor
131
. Similarly, because the gate and drain terminals of NMOS transistor
141
are coupled to the gate terminal of NMOS transistor
142
, NMOS transistor
141
is biased into conduct
Bever, Esq. Patrick T.
Han Jessica
Xilinx , Inc.
Young Edel M.
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