Voltage detection level correction circuit and semiconductor...

Details Voltage detection level correction circuit and semiconductor... Voltage detection level correction circuit and semiconductor...

2002-12-02

2004-06-08

Riley, Shawn (Department: 2838)

Static information storage and retrieval

Powering

C365S189090, C365S145000

Reexamination Certificate

active

06747907

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a voltage detection level correction circuit using a non-volatile memory and to a semiconductor device on which this circuit is mounted.
2. Description of Prior Art
A ferroelectric memory (FeRAM) makes possible reading and writing at a low voltage, as well as high speed operation, in comparison with other non-volatile memories (for example, flash memory or EEPROM). In contrast to this, there is a possibility wherein data rewrite may be carried out even under the condition of a voltage lower than that of a product specification and, therefore, a measure, exceeding the product specification, for preventing malfunction is introduced in the circuit from the point of view of data protection such that a power supply voltage detection circuit is mounted and a command from the outside is not accepted in the case of a voltage lower than, or including, the set voltage.
FIG. 10
shows a block diagram of a semiconductor device on which a ferroelectric memory, which has been conventionally utilized, is mounted. A reference potential generation circuit is denoted as
101
, a reference potential output node of the reference potential generation circuit
101
is denoted as NBGRA, a divided voltage potential generation circuit for generating a divided voltage potential is denoted as
102
, an output node of the divided voltage potential generation circuit
102
is denoted as NHALA, a differential amplification circuit for generating an output PORA at a CMOS level by amplifying a potential difference between output node NBGRA of reference potential generation circuit
101
and output node NHALA of divided voltage potential generation circuit
101
is denoted as
103
, the output node of the differential amplification circuit
103
is denoted as PORA and a power supply voltage detection circuit formed of the reference potential generation circuit
101
, the divided voltage potential generation circuit
102
and the differential amplification circuit
103
is denoted as
104
. A ferroelectric memory for storing arbitrary information is denoted as
105
. A microcomputer logic unit for controlling the ferroelectric memory
105
is denoted as
106
.
In the present circuit, in the case that the power supply voltage is lower than the set level, that is to say, in the case that the potential level of node NBGR is higher than the potential level of node NHALA, the logic level of node PORA is set at “H” so that the ferroelectric memory
105
and the microcomputer logic unit
106
are converted to the deactivated condition. In addition, in contrast to this, in the case that the power supply voltage is higher than the set level, that is to say, the potential level of node NBGR is lower than the potential level of node NHALA, the logic level of node PORA is set at “L” so that the ferroelectric memory
105
and the microcomputer logic unit
106
are converted to the activated condition.
FIG. 11
is a block diagram of a band gap reference circuit showing one example of a reference potential generation circuit.
P channel type CMOS transistors are denoted as QP
101
, QP
102
, QP
103
, QP
104
and QP
105
, N channel type CMOS transistors are denoted as QN
101
, QN
102
, QN
103
and QN
104
, resistor elements are denoted as R
101
, R
102
and R
103
, a differential amplification circuit for amplifying the potential difference between internal nodes N
101
and N
103
formed of transistors QP
103
, QP
104
, QP
105
, QN
102
, and QN
103
is denoted as
107
, diodes are denoted as Di
101
and Di
102
and the ground voltage is denoted as VSS.
The source of P channel type CMOS transistor QP
101
is connected to power supply voltage VDD, and the gate and the drain are connected to node N
104
. The source of P channel type MOS transistor QP
102
is connected to power supply voltage VDD, the gate is connected to node N
104
, and the drain is connected to node NBGRA. The source of P channel type MOS transistor QP
103
is connected to power supply voltage VDD, the gate is connected to node N
104
, and the drain is connected to N
105
. The source of P channel type MOS transistor QP
104
is connected to node N
105
, the gate is connected to node N
101
and the drain is connected to N
106
. The source of P channel type MOS transistor QP
105
is connected to node N
105
, the gate is connected to node N
103
and the drain is connected to N
107
.
The gate of N channel type CMOS transistor QN
101
is connected to node NBIAS, the source is connected to ground voltage VSS and the drain is connected to node N
104
. The gate and the drain of N channel type CMOS transistor QN
102
are connected to node N
106
and the source is connected to ground voltage VSS. The gate of N channel type CMOS transistor QN
103
is connected to node N
106
, the source is connected to ground voltage VSS and the drain is connected to node N
107
. The gate of N channel type CMOS transistor QN
104
is connected to node N
107
, the source is connected to ground voltage VSS and the drain is connected to node NBGRA.
As for the potential supplied to node NBIAS, a potential slightly higher than the threshold value (Vt) of QN
101
is inputted to node NBIAS so that this input allows a constant current to flow through QN
101
.
The differential amplification circuit
107
is formed of transistors QP
103
, QP
104
, QP
105
, QN
102
and QN
103
and has nodes N
101
and N
103
as input terminals, and node N
107
as an output terminal. In the case that the level of node N
103
is higher than that of node N
101
, logic potential “L” is generated at node N
107
and, on the other hand, in the case that the level of node N
103
is lower than that of node N
101
, logic potential “H” is generated.
One end of resistor element R
101
is connected to node NBGRA and the other end is connected to node N
101
. One end of resistor element R
102
is connected to node N
101
and the other end is connected to node N
102
. One end of resistor element R
103
is connected to node NBGRA and the other end is connected to node N
103
.
The P type diffusion region of diode Di
101
is connected to node N
103
and the N type diffusion region is connected to ground voltage VSS. The P type diffusion region of diode Di
102
is connected to node N
102
and the N type diffusion region is connected to ground voltage VSS.
The output voltage VREF at node NBGRA of the band gap reference circuit, shown in
FIG. 11
, is shown in the following equation (equation 1-1) when the threshold voltage of diode Di
101
is denoted as Vd, the resistance values of resistor elements R
101
, R
102
and R
103
, respectively, are rs
11
, rs
12
and rs
13
and the saturation currents of diodes Di
101
and Di
102
, respectively, are Is
11
and Is
12
.
VREF=Vd+
(
rs
11
/
rs
12
)*(
k/q
)*
In{
(
Is
12
/
Is
11
)*(
rs
11
/
rs
13
)}*
T
  (equation 1-1)
wherein the Boltzmann coefficient is denoted as k, the amount of charge of electrons is denoted as q and the absolute temperature is denoted as T.
Vd shown above is dependent on the temperature and has a negative inclination wherein the higher the temperature is, the lower Vd is, while, the lower the temperature is, the higher Vd is.
When the constant voltage portion of the first term, Vd, of the right-side member of (equation 1-1) is denoted as A
1
, the fluctuation portion thereof due to temperature is denoted as &agr;T, the constant voltage portion of the second term of the right-side member of (equation 1-1) is denoted as B
1
, and the fluctuation portion thereof due to temperature is denoted as &bgr;T, VREF is indicated in the following equation (equation 1-2).
VREF=A
1
+
B
1
−&agr;
T+&bgr;T
  (equation 1-2)
The configuration makes it possible to gain a constant reference voltage wherein the dispersion due to the process and to temperature is greatly reduced by setting the values of coefficient &agr; and &bgr;, which are dependent on the temperature, to be equal to each other in (equation 1-2). Though in the present description the circ

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