Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-03-12
2003-03-25
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06538482
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a voltage detection circuit for detecting a power-supply voltage or the like, a power-on/off reset circuit, and a semiconductor device.
BACKGROUND OF THE INVENTION
Recently, a technique has become popular for operating a semiconductor device in a stable condition in a wide power-supply voltage range by changing the internal circuit operation in accordance with the power-supply voltage value. For this reason, a voltage detection circuit for detecting a power-supply voltage value has become important.
A conventional voltage detection circuit will be explained hereinafter with reference to
FIGS. 23-25
.
FIG. 23
shows the construction of the conventional voltage detection circuit.
FIG. 24
shows the relationship between the power-supply voltage and the output voltage signal in the conventional voltage detection circuit.
FIG. 25
shows the relationship between the power-supply voltage and the current drain.
Firstly, the circuit construction will be explained. As shown in
FIG. 23
, the Qp
61
is a P-channel type MOS transistor whose source is connected with the power-supply voltage VDD and whose gate and train are connected with the node N
61
. The Qp
62
is a P-channel type MOS transistor whose source is connected with the node N
61
and whose gate and train are connected with the node N
62
. The Qp
63
is a P-channel type MOS transistor whose source is connected with the node N
62
and whose gate and train are connected with the node N
63
. The Qn
61
is an N-channel type MOS transistor whose source is connected with the ground voltage VSS, whose gate is connected with the power-supply voltage VDD, and whose train is connected with the node N
63
. The Qp
64
is a P-channel type MOS transistor and the Qn
62
is an N-channel type MOS transistor which compose a first NOT circuit
61
. The source, gate, and drain of the P-channel type MOS transistor Qp
64
are connected with the ground voltage VDD, the node N
63
, and the node N
64
, respectively. The source, gate, and drain of the N-channel type MOS transistor Qn
62
are connected with the ground voltage VSS, the node N
63
, and the node N
64
, respectively. The node N
64
is connected with the input terminal of a second NOT circuit
62
. The second NOT circuit
62
is applied with the voltage detection signal VDT
60
from the node N
64
, and generates the output voltage signal VOUT
60
.
The operation of the voltage detection circuit will be explained as follows. As shown in
FIG. 24
, the logical voltage of the output voltage signal VOUT
60
which is obtained at the output terminal of the second NOT circuit
62
becomes “L” when the power-supply voltage VDD is less than 4V and becomes “H” when the voltage VDD is about 4V or higher under predetermined conditions.
This result is due to the following ground. The electric potential of the node N
63
is lower than the power-supply voltage VDD by the voltage drop of the P-channel type MOS transistors Qp
61
-Qp
63
. The electric potential becomes 2V, for example.
On the other hand, the threshold level of the first NOT circuit
61
which is composed of the P-channel type MOS transistor Qp
64
and the N-channel type MOS transistor Qn
62
is about ½ of the power-supply voltage VDD. Therefore, when the power-supply voltage VDD is about 4V, the electric potential of the node N
64
which is connected with the input terminal of the first NOT circuit
61
becomes about 2V, so that the logical voltage of the node N
64
, or the voltage detection signal VDT goes from “H” to “L”, and the logical voltage of the output voltage signal VOUT
60
which is the output of the second NOT circuit
62
goes from “L” to “H”.
The current drain of the voltage detection circuit will be explained as follows. As shown in
FIG. 24
, when the power-supply voltage VDD is about 4V, the node N
63
which is the input terminal of the first NOT circuit
61
consisting of the P-channel type MOS transistor Qp
64
and the N-channel type MOS transistor Qn
62
has an intermediate electric potential between the power-supply voltage VDD and the ground voltage VSS. Consequently, both the P-channel type MOS transistor Qp
64
and the N-channel type MOS transistor Qn
62
are in the on state, that is, the first NOT circuit
61
temporarily falls into the short-circuit state. The current drain In
60
which runs through the N-channel type MOS transistor Qn
62
has a peak of 0.6 &mgr;A or so. Even when the power-supply voltage VDD is not about 4V, the current drain In
60
is 0.1 &mgr;A or higher as shown in FIG.
25
.
However, in the conventional voltage detection circuit, when the electric potential of the node N
63
which is the input of the-first NOT circuit
61
has an intermediate electric potential between the power-supply voltage VDD and the ground voltage VSS, both the P-channel type MOS transistor Qp
64
and the N-channel type MOS transistor Qn
62
become the on state, that is, fall into temporary short-circuit state, which leads to an increase in the current drain. The current drain for the entire voltage detection circuit is large in other states, too.
In view of these problems, the object of the present invention is to provide a voltage detection circuit which reduces the peak of the current drain in the temporary short-circuit state and decreases the current drain as the entire circuit.
On the other hand, when a predetermined voltage is detected by the voltage detection circuit, a power-on/off reset circuit for immediately suspending the operations of the devices such as a logic circuit or a memory circuit might destroy memory data in the memory circuit when the operation is immediately suspended. Although there is no problem in the logic circuit, the memory circuit needs data re-writing (restore or refresh) after a readout. For this reason, it is difficult to properly terminate a sequence in operation.
In view of these problems, another object of the present invention is to provide a power-on/off reset circuit which properly terminates a sequence in operation.
DISCLOSURE OF THE INVENTION
The present invention includes the voltage detection circuit, power-on/off reset circuit, and semiconductor device which are constructed as follows.
The voltage detection circuit of the invention of claim
1
is characterized by comprising a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node.
The voltage detection circuit of the invention of claim
2
comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node and whose output terminal is a fourth node, a second NOT circuit whose input terminal is connected with the fourth node, whose output terminal is a fifth node, and which is connected between a third node and the ground voltage terminal, and a third MOS transistor whose gate is connected with the fifth node and which is connected between either the ground voltage terminal or the power-supply voltage terminal and the fourth node.
In the invention of claim
3
, the first, second, and third MOS transistors of th
Asari Kouji
Hirano Hiroshige
Sumi Tatsumi
Cunningham Terry D.
RatnerPrestia
Tra Quan
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