Voltage dependent capacitor configuration for higher soft...

Details Voltage dependent capacitor configuration for higher soft... Voltage dependent capacitor configuration for higher soft...

2000-06-29

2003-04-22

Vu, Bao Q. (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C365S149000, C365S184000

Reexamination Certificate

active

06552887

ABSTRACT:

FIELD OF INVENTION
The invention relates generally to integrated circuits. In particular, the invention relates to reducing soft errors in integrated circuits.
BACKGROUND OF THE INVENTION
The operating voltage of a high-speed microprocessor is being reduced as process technology scales. For example, microprocessor device dimensions are shrinking and integrated circuit (IC) chips are operating at increasing frequencies. As a result, IC chips are becoming more susceptible to external interferences. Interference may be caused by cosmic rays, or by spurious noise, for example.
These noise sources can cause soft errors in memories and storage elements in the IC chips when they are used at high altitudes in aerospace applications. Also, the noise sources can cause soft errors in IC chips even at ground levels. A conventional capacitor does not adjust itself to fight a node charge injection by noise sources. Consequently, storage elements in data paths of an IC chip, such as static latches and dynamic gates for example, are becoming susceptible to the soft error rate (SER) caused by noise sources.


REFERENCES:
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patent: 4839865 (1989-06-01), Sato et al.
patent: 4991137 (1991-02-01), Matsumoto
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patent: 5303190 (1994-04-01), Pelley, III
patent: 5324961 (1994-06-01), Rodder
patent: 5726944 (1998-03-01), Pelley et al.

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