Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-03-30
2008-03-11
Nguyen, Jimmy H. (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S076000, C345S211000, C315S169300
Reexamination Certificate
active
07342560
ABSTRACT:
In case an input voltage is zero, to sufficiently shut off an output current, a source side of a first transistor T1is connected to the drains of fourth and fifth transistors T4and T5, and during a self-bias period of the first transistor T1, a source of the first transistor T1is made a second potential through the fourth transistor T4, and in a gate potential setting period of the first transistor T1by an input voltage Vin after the completion of the self-bias period, the source of the first transistor T1is made a third potential through the fifth transistor T5.
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Kondo Shigeki
Nakajima Yoshinori
Yuki Osamu
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Nguyen Jimmy H.
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