Voltage/current controller device, particularly for...

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

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C323S282000

Reexamination Certificate

active

06628110

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage/current controller device, particularly for interleaving switching regulators.
Specifically, the invention relates to a controller device as above, which comprises a DC/DC converter having a plurality of modules, each module including a pair of drive transistors connected in series between first and second supply voltage references, a current sensor connected to one transistor in said pair, and a current reading circuit connected to said sensor.
The invention relates, particularly but not exclusively, to a controller device for switching regulators of the interleaving type as used in computer processors, this description making reference to this field of application for convenience of illustration only.
2. Description of the Related Art
As is well known, developments in the electrical characteristics of computer processors, e.g, PC, WORKSTATION, and SERVER, are compelling the manufacturers to seek new solutions in order to meet the requirements of central processing units (CPUs).
In particular, CPUs require an accurately adjusted supply voltage (±0.8% at steady state, ±3% in transient conditions).
However, supply voltages as low as 1.1 V, and load currents of up to 100 A, with 100 A/&mgr;s edges, are used at present. This requires a higher efficiency than 80%.
So it is that current or voltage control devices must be employed, which can assure of the necessary efficiency. To fill the above demands, a low-cost device of this kind may comprise an interleaving type of DC/DC converter, for example.
In particular, this converter layout is obtained by connecting in parallel N DC/DC converters in a step-down configuration, i.e., with the voltage input and output connected together. Each DC/DC converter is referred to as the “module” or “channel”.
An interleave configuration needs a synchronization circuit to close the high-side switches of the converter modules with a phase shift equal to the switching period divided by the number N of modules.
For simplicity, reference will be made hereinafter to a DC/DC converter having two interleaving modules.
It should be noted that when a conventional voltage mode control is applied to an interleaving type of converter an uncontrolled distribution of the currents flowing through the inductors of the parallel modules is produced. Thus, to perform satisfactorily, the converter requires that the total load current be split equally among the modules, i.e., that each module carried a current equal to the target output current divided by N. This control technique is known as “current sharing”.
Additionally to said current-sharing option, interleaving DC/DC converters are required to vary the output voltage level proportionally to the target output current. In other words, with Vout,nom being the rated output voltage, i.e., the voltage value when the converter is outputting no current, and Iout being the value of the output current, the output voltage level Vout is given as:
Vout=Vout,nom−Iout*K,
where K is a factor decided upon outside the converter.
This option is known as “voltage positioning” or “droop function”.
Conventional converter devices with current-sharing and droop function options are available commercially in several different types.
These devices must also check that the current load, if anomalous, does not damage the equipment which is power supplied by the dc—dc converter. Over-current, or even short-circuit, conditions are load degeneration conditions which must be detected and solved by the control system in order to protect itself and the load. As it is evident, the voltage positioning and current sharing systems, as well as protection systems against over-current and short-circuit conditions require an efficient reading and processing system of the analog information “current of each phase”.
Such options involve the need for a converter operative to read or estimate the output current from each module. In particular, the DC/DC converter is to include a read circuit arranged to read this module current by the voltage drop across an output resistor. This resistor may be parasitic to the circuit, e.g., the power switch resistance Rds,on or the DCR of an inductor, or be an element deliberately introduced in the read circuit and usually designated Rsense.
Using a dedicated resistive element Rsense is advantageous in that the reading obtained is highly accurate and unaffected by temperature (e.g., using resistors made of constantan). It has, however, the disadvantages of being expensive and providing a less efficient current-to-voltage conversion within the converter.
On the other hand, utilizing a parasitic element inside the read circuit is surely more cost-efficient, since existing elements in the read circuit can be used. However, this solution lowers reading accuracy because it responds to both manufacturing variations and operating temperatures.
Illustrated schematically by
FIGS. 1
to
4
are different conditions in the operation of an interleaving DC/DC converter according to the prior art.
Assume for simplicity the target output current Iout to have been split equally among the N converter modules.
FIG. 1
shows schematically an interleaving DC/DC converter
1
that comprises at least one module
2
, in turn comprising a high-side transistor M
HS
and a low-side transistor M
LS
connected in series together between a first or supply voltage reference VDD and a second or ground voltage reference GND. The module
2
is connected to a load comprising a network
3
, in turn connected between a terminal X intermediate the transistors M
HS
, M
LS
and ground GND.
This network
3
comprises a series of an inductor L and a capacitor C.
Illustrated schematically in
FIG. 1
is a working condition in which the reading performed is a current reading effected across the drain and source terminals of the high-side transistor M
HS
.
In this case, the reading is little dissipative. Being Iout,
2
the average current from any module
2
, i.e., the average current through the inductor L in the network
3
, the power dissipated through the DC/DC converter
1
having N modules will be:
D*N*Rds,on*(Iout,2)
2
where D is the ratio of the output voltage value Vout to the value of the supply voltage VDD of the DC/DC converter
1
(D=Vout/Vin). The ratio D is, therefore, quite small, in particular between 1V/12V and 1.85V/12V.
In conventional converters, the high-side transistor M
HS
will close for a time duration D*Ts (where Ts is the switching period of the converter
1
). This duration is very small, however.
Also, when the high-side transistor M
HS
closes and its source terminal reaches a value equal to an input voltage Vin, the reading becomes injured by noise from capacitive coupling effects.
All this makes for difficult reading.
FIG. 2
likewise shows a working condition in which a current reading is performed across the drain and source terminals of the low-side transistor M
LS
.
In this case, the reading is little dissipative, and the power dissipated is:
N*Rds,on*(1−D)*[Iout,2]
2
.
The low-side transistor M
LS
will close for a time duration (1−D)*Ts. This time allows a reading to be completed even with conventional converters. For example, a resistive element Rsense in series with the low-side transistor M
LS
may be used.
FIG. 3
shows schematically a working condition in which a current reading is performed across the inductor L of the network
3
.
In this case, the reading is dissipative, the power dissipated being:
N*DCR*Iout,2
2
where DCR is the equivalent resistance of the inductor L in the network
3
.
It should be noted, however, that the intermediate node X, being connected to one end of the inductor, would exhibit voltage values within the range of ground reference GND to input voltage Vin. Thus, the reading must be made by filtering the voltage signal at the node X to extract continuous information. This filtering introduces new components, and injures the overall speed of

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