Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2001-11-13
2003-09-09
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S175000, C327S035000
Reexamination Certificate
active
06617898
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage conversion circuit for supplying a driving voltage to an integrated circuit, and relates also to a semiconductor integrated circuit device provided with such a voltage conversion circuit.
2. Description of the Prior Art
In general, an integrated circuit that performs arithmetic or other operation in synchronism with an operation clock is designed with ample margins in its specifications to ensure that it operates normally even when there are variations in its characteristics that are inevitable in its manufacturing process or fluctuations in the supplied voltage or in the ambient temperature. Specifically, an integrated circuit is so designed that, even when the delay it produces increases as a result of a variation or fluctuation such as mentioned above or any other factor, an operation of the integrated circuit as a whole is complete within one clock of the operation clock. Moreover, a sufficiently high supply voltage is supplied to the integrated circuit so that it operates normally even when all the factors mentioned above are in the worst condition.
Designing an integrated circuit with ample margins in its specifications and applying a sufficiently high supply voltage to it as described above, however, make it difficult to enhance its speed and to reduce its power consumption. For this reason, efforts have been made to develop a voltage conversion circuit that controls a supply voltage according to the operation status of an integrated circuit so that the integrated circuit is fed with the minimum driving voltage it requires to operate at a given time.
FIG. 21
is a diagram schematically showing an example of the circuit configuration of a conventional voltage conversion circuit. The voltage conversion circuit shown in
FIG. 21
is disclosed in Japanese Patent Application Laid-Open No. H10-242831, and is composed of a duty factor control circuit
901
, a buffer circuit
902
, a filter circuit
903
, a critical path circuit
904
, a delay circuit
905
, a true/false evaluation circuit
906
, and an adder
907
.
The duty factor control circuit
901
is a circuit that controls the varying of an output voltage in the buffer circuit
902
, and is composed of a counter and a comparator. The counter counts up from 0 to 2
n−1
(for example, when n=6, from 0 to 63) in increments of 1 in synchronism with every period of a clock signal (not shown) fed to it, and feeds its count, in the form of an n-bit signal NA, to the comparator. The count that follows 2
n−1
is 0. The comparator is fed with, in addition to the signal NA, another n-bit signal NB from the adder
907
.
The comparator is a circuit that controls the on/off state of a PMOS transistor M
1
and an NMOS transistor M
2
that together constitute the buffer circuit
902
. The comparator feeds control signals X
1
and X
2
to the gates of the transistors M
1
and M
2
respectively. When the signal NA equals 0, the comparator turns the voltage levels of the control signals X
1
and X
2
to a low level (hereinafter “L level”); when the signals NA and NB are equal, the comparator turns the voltage levels of the control signals X
1
and X
2
to a high level (hereinafter “H level”).
In the buffer circuit
902
, a first supply voltage is applied to the source of the PMOS transistor M
1
, and a second supply voltage (here the ground voltage) is applied to the source of the NMOS transistor M
2
. The two transistors have their drains connected together, with the node between them serving as the output end of the buffer circuit
902
.
Accordingly, when the control signals X
1
and X
2
are at L level, the PMOS transistor M
1
is on and the NMOS transistor M
2
is off. Thus, the output voltage of the buffer circuit
902
is nearly equal to the first supply voltage. By contrast, when the control signals X
1
and X
2
are at H level, the PMOS transistor M
1
is off and the NMOS transistor M
2
is on. Thus, the output voltage of the buffer circuit
902
is nearly equal to the second supply voltage (i.e. the ground voltage). That is, the output voltage of the buffer circuit
902
is a pulsating voltage signal Y that rises when the signal NA turns to 0 and that falls when the signal NA becomes equal to the signal NB.
This voltage signal Y is smoothed by the filter circuit
903
composed of an inductor L
1
and a capacitor C
1
, and is thereby formed into an output voltage Z. The output voltage Z is supplied to an internal circuit (not shown) formed on the same circuit board so as to be used as the driving voltage for the internal circuit. The output voltage Z is used also as the supply voltage for the critical path circuit
904
.
In the buffer circuit
902
, let the period in which the PMOS transistor M
1
is on and the NMOS transistor M
2
is off (i.e. the period in which the control signals X
1
and X
2
are at L level) be called the on period T
1
, and let the period in which the PMOS transistor M
1
is off and the NMOS transistor M
2
is on (i.e. the period in which the control signals X
1
and X
2
are at H level) be called the off period T
2
. Then, the output voltage Z of the filter circuit
903
is generally given by
Z
=
T1
T1
+
T2
×
VDD
(
1
)
In the formula above, the on period T
1
(the numerator in the right side) represents the pulse width of the voltage signal Y, and the sum T
1
+T
2
of the on period T
1
and the off period T
2
(the denominator in the right side) represents the pulse period of the voltage signal Y. That is, the output voltage Z can be controlled by controlling the ratio of the pulse width to the pulse period of the voltage signal Y (hereinafter this ratio will be referred to as the “duty factor”).
In the voltage conversion circuit configured as described above, the value of the signal NB fed from the adder
907
to the comparator of the duty factor control circuit
901
is varied to vary the on period T
1
(the pulse width) and thereby control the duty factor of the voltage signal Y output from the buffer circuit
902
. In this way, it is possible to control the driving voltage (the output voltage Z) fed to the internal circuit. (In the following descriptions, this method of controlling the duty factor is called the variable pulse width method.) Moreover, as a means for setting the signal NB at the optimum value at a given time, the operation speed of the critical path circuit
904
is detected.
The critical path circuit
904
is a duplicate circuit of the path that is considered to produce the longest delay within the internal circuit to which the output voltage Z is fed. As described earlier, the output voltage Z of the filter circuit
903
is applied to the critical path circuit
904
as the supply voltage for it. That is, the driving voltage for the internal circuit, i.e. the destination of the voltage supply, is monitored by the critical path circuit
904
. Here, it is assumed that the range of voltages on which the critical path circuit
904
can operate is equal to that on which the internal circuit can operate.
When the critical path circuit
904
can operate on the output voltage Z of the filter circuit
903
, the critical path circuit
904
feeds predetermined data to the true/false evaluation circuit
906
. Here, the true/false evaluation circuit
906
receives the data not only directly from the critical path circuit
904
, but also with a delay through the delay circuit
905
.
If the true/false evaluation circuit
906
does not receive the data directly from the critical path circuit
904
, the true/false evaluation circuit
906
judges that the internal circuit, i.e. the destination of the voltage supply, is not operating normally, and therefore judges that the driving voltage for the internal circuit (i.e. the output voltage Z of the filter circuit
903
) is too low. Thus, the true/false evaluation circuit
906
feeds the adder
907
with a signal S
1
that instructs it to increment the value of the signal NB by 1 to increase the driving voltage.
If the true/false eval
Okuno Tomohisa
Sato Yuichi
Callahan Timothy P.
Luu An T.
Sharp Kabushiki Kaisha
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