Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2003-05-28
2004-03-23
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
Reexamination Certificate
active
06710638
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage conversion circuit and a semiconductor device using the same. More particularly, the present invention relates to a voltage conversion circuit for converting signal voltage levels between circuits having different power source voltages and a semiconductor device using the same.
2. Description of the Related Art
Conventionally, when a signal is transferred between circuits having different power source voltages, a voltage conversion circuit (level shifter circuit) which converts the amplitude levels of signal voltages between these circuits is used as an interface circuit.
For example, the circuit configuration and operation of a voltage conversion circuit will be described below, which has a plurality of circuit sections comprising MOS transistors and driven by different power source voltages and which functions as an interface circuit.
FIG. 7
is a circuit diagram showing a voltage conversion circuit
100
which functions as the above-described interface circuit. The voltage conversion circuit
100
comprises an inverter circuit
70
and a voltage output circuit
80
.
The power source voltage and reference voltage (LOW level) of the voltage output circuit
80
are VDD1 and VSS1, respectively. The power source voltage and reference voltage (LOW level) of the inverter circuit
70
are VDD2 and VSS1, respectively. Here, voltage conditions are VDD1>VDD2 and VSS1=VSS2=GND level. These conditions are referred to as voltage conditions A.
In the voltage output circuit
80
, P-type MOS transistors
80
c
and
80
d
are connected in parallel. The source terminals of the P-type MOS transistor
80
c
and
80
d
are each connected to the power source voltage VDD1. The drain terminals of the P-type MOS transistors
80
c
and
80
d
are connected to the drain terminals of N-type MOS transistors
80
a
and
80
b
, respectively. The gate terminals of the P-type MOS transistors
80
a
and
80
d
are connected to the drain terminals of the N-type MOS transistors
80
b
and
80
a
, respectively. The drain terminals of the P-type MOS transistor
80
d
and the N-type MOS transistor
80
b
are the output terminal (output node B) of the voltage conversion circuit
100
. The source terminals of the N-type MOS transistors
80
a
and
80
b
are each connected to VSS1=GND (earth). The gate terminal of the N-type MOS transistor
80
a
is connected to the input terminal of the inverter circuit
70
. The gate terminal of the N-type MOS transistor
80
b
is connected to the output terminal of the inverter circuit
70
.
The inverter circuit
70
comprises a P-type MOS transistor
70
b
and the N-type MOS transistor
70
a
. The drain and gate terminals of the P-type MOS transistor
70
b
are connected to the drain and gate terminals of the N-type MOS transistor
70
a
, respectively. The drain terminals of the P-type MOS transistor
70
b
and the N-type MOS transistor
70
a
are each the output terminal of the inverter circuit
70
, while the gate terminals of the P-type MOS transistor
70
b
and the N-type MOS transistor
70
a
are each the input terminal of the inverter circuit
70
. The input terminal of the inverter circuit
70
is the input terminal (input node A) of the voltage conversion circuit
100
. The source terminals of the P-type MOS transistor
70
b
and the N-type MOS transistor
70
a
are connected to the power source voltage VDD2 and VSS2=GND (earth), respectively.
In the voltage conversion circuit
100
of
FIG. 7
, when a signal voltage A (HIGH level: VDD2, LOW level: VSS2) is input to the input node A, a signal voltage B (HIGH level: VDD1, LOW level: VSS1) is output through the output node B so that the HIGH level (VDD2) of the signal voltage A is converted to the HIGH level (VDD1) of the signal voltage B (voltage conversion). This operation will be described below in more detail. Note that the HIGH level and the LOW level are referred to as the H state and the L state, respectively.
It is now assumed that the input node A is in the H (VDD2) state. In this case, the input terminal of the inverter circuit
70
and the gate terminal of the N-type MOS transistor
80
a
of the voltage output circuit
80
are in the H state, and the N-type MOS transistor
80
a
is in the ON state. In this case, the output terminal of the inverter circuit
70
is in the L state, while the drain terminal of the N-type MOS transistor
80
a
is in the L state. When the output terminal of the inverter circuit
70
is in the L state, the gate terminal of the N-type MOS transistor
80
b
is in the L state, so that the N-type MOS transistor
80
b
is in the OFF state and the drain terminal of the N-type MOS transistor
80
b
is in the H state.
When the drain terminal of the N-type MOS transistor
80
b
is in the H state, the gate terminal of the P-type MOS transistor
80
c
is also in the H state and the P-type MOS transistor
80
c
is in the OFF state. In this case, the power source voltage VDD1 of the voltage output circuit
80
is not applied to the drain terminal of the N-type MOS transistor
80
a
, so that the drain terminal of the N-type MOS transistor
80
a
is maintained in the L state.
When the drain terminal of the N-type MOS transistor
80
a
is in the L state, the gate terminal of the P-type MOS transistor
80
d
is also in the L state, so that the P-type MOS transistor
80
d
is in the ON state. In this case, the power source voltage VDD1 of the voltage output circuit
80
is applied to the drain terminal of the N-type MOS transistor
80
b
. In this case, the N-type MOS transistor
80
b
is in the OFF state, while the H state (VDD1) of the drain terminal of the N-type MOS transistor
80
b
is output through the output terminal (output node B).
The same applies to the case where the input node A is in the L (VSS2) state. In this case, the output node B is in the L (VSS1) state, where VSS1=VSS2=GND.
Next, only an inverter circuit is provided between the circuits having different power source voltages instead of the voltage conversion circuit
100
. The operation of this circuit
110
configuration will be described below with reference to FIG.
8
.
The inverter circuit
110
of
FIG. 8
comprises a P-type MOS transistor
90
b
and an N-type MOS transistor
90
a
. The drain and gate terminals of the P-type MOS transistor
90
b
are connected to the drain and gate terminals of the N-type MOS transistor
90
a
, respectively. The drain terminals of the P-type MOS transistor
90
b
and the N-type MOS transistor
90
a
are the output terminal (output node B) of the inverter circuit
110
. The gate terminals of the P-type MOS transistor
90
b
and the N-type MOS transistor
90
a
are the input terminal (input node A) of the inverter circuit
110
. The source terminals of the P-type MOS transistor
90
b
and the N-type MOS transistor
90
a
are connected to the power source voltage VDD1 and VSS1=GND (earth), respectively.
It is now assumed that a signal voltage A (H: VDD2, L: VSS2) satisfying the above-described voltage conditions A (VDD1>VDD2 and VSS1=VSS2=GND level) is applied to the input node A of the inverter circuit
110
. The operation of the inverter circuit in this case will be described.
When a potential difference between VDD1 and VDD2 (=VDD1-VDD2) is less than a threshold voltage of the P-type MOS transistor
90
b
of
FIG. 8
, if an H state (VDD2) signal voltage A is input to the input node A, the P-type MOS transistor
90
b
is in the OFF state. In this case, the N-type MOS transistor
90
a
is in the ON state and the output node B is in the L state (VSS1). Alternatively, when an L state (VSS2) signal voltage A is input to the input node A, the P-type MOS transistor
90
b
is in the ON state and the N-type MOS transistor
90
a
is in the OFF state, so that the output node B is in the H state (VDD1). In this case, the inverter circuit is normally operated to perform voltage conversion (VDD2→VDD1) between the input node A and th
Birch & Stewart Kolasch & Birch, LLP
Nuton My-Trang
Sharp Kabushiki Kaisha
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