Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
2000-11-07
2002-04-02
Nguyan, Matthew (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
C327S535000
Reexamination Certificate
active
06366482
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage conversion circuit, and in particular to an improved voltage conversion circuit that can reduce a layout area and power consumption and improve conductivity and reliability, by efficiently driving a pumping capacitor by receiving an oscillation signal applied during a voltage pumping operation and using transitions from high to low and from low to high without overlapping each driving signal through a flip-flop switching structure, and by solving reduction of a threshold voltage of an NMOS transistor by controlling a precharge and switching transistor with a PMOS transistor.
2. Description of the Background Art
A voltage conversion circuit was disclosed on May 28, 1996 by Keum-Yong Kim under U.S. Pat. No. 5,521,546 “Voltage boosting circuit constructed on an integrated circuit substrate, as for a semiconductor memory device”.
FIG. 1
attached to the present specification is adopted from the U.S. Pat. No. 5,521,546.
FIG. 1
is a circuit diagram illustrating a conventional voltage conversion circuit for supplying a boosting voltage VPP to a semiconductor memory device. As shown therein, the voltage conversion circuit includes: a boosting oscillation unit
10
for generating a clock signal having a predetermined period, when the semiconductor memory device is powered up or the boosting voltage VPP is below a desired level; a main pumping unit
20
for receiving an output VPPOSC of the boosting oscillation unit
10
, and pumping from the power supply voltage VCC in order to generate a desired boosting voltage VPP; first and second transmission gates
31
,
32
for alternately outputting an output from the main pumping unit
20
; first and second switching control unit
41
,
42
for controlling a switching operation of the first and second transmission gates
31
,
32
according to the output from the main pumping unit
20
; a well bias supply unit
50
for supplying a bias set in an isolation well formed at the channels of the first and second transmission gates
31
,
32
; a well bias oscillation unit
60
for generating a clock signal having a predetermined period in order to drive the well bias supply unit
50
, when the semiconductor memory device is powered up or the boosting voltage VPP is below a desired level; and a boosting node
70
formed by commonly connecting the output terminals of the first and second transmission gates
31
,
32
in order to supply a desired boosting voltage VPP.
Here, when it is presumed that the conventional voltage conversion circuit is formed on a P-type substrate, the first and second transmission gates
31
,
32
are respectively formed in an N-type isolation well as a PMOS transistor, and the well bias supply unit
50
supplies the predetermined bias to the isolation well where the first and second transmission gates
31
,
32
consisting of the PMOS transistors are formed.
The well bias oscillation unit
60
and the well bias supply unit
50
supply the predetermined bias to the wells of the first and second transmission gates
31
,
32
before starting the pumping operation, so that the voltage conversion circuit can perform the stable and precise boosting operation.
While the semiconductor memory device that is provided with the power supply voltage VCC at an initial stage is powered up, the well bias oscillation unit
60
is activated, and thus the well bias supply unit
50
is driven. A well voltage of the first and second transmission gates
31
,
32
are generated by the well bias supply unit
50
. Here, the voltage is applied to the wells of the first and second transmission gates
31
,
32
for the stable operation of the voltage conversion circuit.
Thereafter, when the driving signal VCCH is enabled, the boosting oscillation unit
10
is activated, the boosting voltage VPP is increased to a desired level, and thus the main pumping unit
20
is enabled. The pumped voltage is transmitted as the boosting voltage VPP to the boosting node
70
through the channels of the first and second transmission gates
31
,
32
that are alternately connected under the control of each gate potential provided by the first and second switching control units
41
,
42
.
FIG. 2
is a detailed circuit diagram illustrating major components of the conventional voltage conversion circuit as shown in FIG.
1
. As shown therein, the main pumping unit
20
includes: a first NOR gate
23
having its first input terminal connected to receive a signal outputted from the boosting oscillation unit
10
and delayed by first and second inverters
21
,
22
that are connected in series, and having its second input terminal connected to receive the output signal from the boosting oscillation unit
10
; a first NAND gate
26
having its first input terminal connected to receive an output from the first NOR gate
23
, and having its second input terminal connected to receive a signal outputted from the first NOR gate
23
and delayed by third and fourth inverters
24
,
25
; a fifth inverter
27
for inverting an output from the first NAND gate
26
; a first pumping capacitor
30
having its first terminal connected to receive a signal outputted from the first NOR gate
23
and delayed by sixth and seventh inverters
28
,
29
, and having its second terminal connected to a first node
81
connected to a source of the first transmission gate
31
; a second NAND gate
33
having its first input terminal connected to receive a signal VPPOSC outputted from the boosting oscillation unit
10
and delayed by the first and second inverters
21
,
22
, and having its second input terminal connected to receive the output signal VPPOSC from the boosting oscillation unit
10
; a seventh inverter
34
for inverting an output from the second NAND gate
33
; a third NAND gate
37
having its first input terminal connected to receive a signal outputted from the seventh inverter
34
and delayed by eighth and ninth inverters
35
,
36
, and having its second input terminal connected to receive the output from the seventh inverter
34
; a tenth inverter
38
.for inverting and outputting an output from the third NAND gate
37
; eleventh and twelfth inverters
39
,
40
for re-delaying the signal delayed by the eighth and ninth inverters
35
,
36
; and a second pumping capacitor
43
having its first terminal connected to receive a signal delayed by the eleventh and twelfth inverters
39
,
40
, and having its second terminal connected to a second node
82
connected to a source of the second transmission gate
32
. Here, the output from the first NAND gate
26
and the signal inverted by the fifth inverter
27
are applied to the first switching control unit
41
as an input signal. The output from the third NAND gate
37
and the signal inverted by the tenth inverter
38
are applied to the second switching control unit
42
as an input signal.
The well bias supply unit
50
includes: first and second inverter
51
,
52
for sequentially inverting an output signal WELLOSC of the well bias oscillation unit
60
; first and second capacitors
53
,
54
having their first terminals connected to receive an output from the first inverter
51
; third and fourth capacitors
55
,
56
having its first terminals connected to receive an output from the second inverter
52
; first to fourth NMOS transistors
57
,
58
,
59
,
61
connected as resistances in order to apply the power supply voltage VCC to second terminals of the first to fourth NMOS capacitors
53
~
56
; a fifth NMOS transistor
62
connected between the second terminals of the first and third capacitors
53
,
55
and diode-connected; a sixth NMOS transistor
63
connected between the second terminal of the third capacitor
55
and the well node
83
, and diode-connected; a seventh NMOS transistor
64
connected between the second terminals of the second and fourth capacitors
54
,
56
and diode-connected; and an eighth NMOS transistor
65
connected between the second terminal of the fourth capacitor
56
and the well node
83
, and
Birch & Stewart Kolasch & Birch, LLP
Hyundai Electronics Industries Co,. Ltd.
Nguyan Matthew
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