Oscillators – Ring oscillators
Reexamination Certificate
2000-06-28
2001-11-27
Grimm, Siegfried H. (Department: 2817)
Oscillators
Ring oscillators
C331S075000, C331S109000, C331S183000, C331S17700V
Reexamination Certificate
active
06323738
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-186326, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a voltage-controlled oscillator (VCO), and, more particularly, to a ring type voltage-controlled oscillator which uses a plurality of differential delay cells and which is used to generate a high-frequency clock signal for the internal circuits of an LSI, such as a micro computer (MCU: Micro Control Unit) or a digital signal processor (DSP). This voltage-controlled oscillator is adapted to various applications to improve the processing performance of an LSI and suppress the overall power of a system by using a low-frequency clock for an external clock of the LSI and a high-frequency clock for an internal clock of the LSI.
FIG. 1
shows a conventional fundamental voltage-controlled oscillator which uses a plurality of differential delay cells. This oscillator includes a level converting circuit and amplitude controller
1
, differential delay cells
2
to
6
, which constitute a voltage-controlled oscillation section
100
, and an output level converting circuit
7
. The delay cells
2
to
6
have the same circuit structure which comprises PMOS (P channel MOS) transistors P
1
and P
2
and NMOS (N channel MOS) transistors N
1
to N
3
. The voltage-controlled oscillator performs its oscillating operation as the differential output signals of the first-stage delay cell
2
are sequentially supplied to the subsequent stages of delay cells
3
,
4
and
5
and the differential output signals, Vip and Vim, of the last-stage delay cell
6
are supplied to the output level converting circuit
7
and are fed back to the gates of the NMOS transistors N
2
and N
1
in the first-stage delay cell
2
. An amplitude control voltage Vbp output from the level converting circuit and amplitude controller
1
is supplied to the gates of the PMOS transistors P
1
and P
2
in each of the delay cells
2
-
6
, and a control voltage Vcn output from the level converting circuit and amplitude controller
1
is supplied to the gate of the NMOS transistor N
3
, thereby controlling the oscillating operation. The output level converting circuit
7
outputs a clock signal CKout. Note that the level converting circuit and amplitude controller
1
, the delay cells
2
-
6
and the output level converting circuit
7
operate on power supply voltages VDD and VSS.
FIG. 2
exemplifies the structure of a level converting circuit
1
A in the circuit shown in
FIG. 1
,
FIG. 3
exemplifies the structure of an amplitude controller
1
B in the circuit shown in FIG.
1
and
FIG. 4
exemplifies the structure of the output level converting circuit
7
in the circuit shown in FIG.
1
.
As shown in
FIG. 2
, the level converting circuit
1
A comprises PMOS transistors P
3
and P
4
, NMOS transistors N
4
and N
5
and a resistor R
1
. This circuit
1
A performs voltage/current conversion of a control voltage Vin input externally and then performs current/voltage conversion to generate the control voltage Vcn. The control voltage Vin is supplied to the gate of the NMOS transistor N
4
and the control voltage Vcn is output from a common node between the drains of the PMOS transistor P
4
and the NMOS transistor N
5
.
The amplitude controller
1
B shown in
FIG. 3
comprises a reference voltage generator
8
, an operational amplifier
9
and an amplitude-control target circuit
101
. The amplitude-control target circuit
101
comprises PMOS transistors P
5
and P
6
and NMOS transistors N
6
to N
8
. A reference voltage Vref output from the reference voltage generator
8
is supplied to the inverting input terminal (−) of the operational amplifier
9
and the gate of the NMOS transistor N
7
. The control voltage Vcn that is output from the level converting circuit
1
A is supplied to the gate of the NMOS transistor N
8
. The output of the operational amplifier
9
is supplied to the gates of the PMOS transistors P
5
and P
6
and is output as the amplitude control voltage Vbp.
As shown in
FIG. 4
, the output level converting circuit
7
comprises PMOS transistors P
7
to P
9
and NMOS transistors N
9
to N
12
. The output signal Vim of the delay cell
6
is supplied to the gate of the NMOS transistor N
9
, and the output signal Vip to the gate of the NMOS transistor N
10
. The clock signal CKout is acquired from a common node between the drains of the PMOS transistor P
9
and the NMOS transistor N
12
.
With the above structure, the control voltage Vin is input to the level converting circuit
1
A where it is converted to the control voltage Vcn according to a control current Icnt of the delay cells
2
-
6
. In the amplitude controller
1
B, the amplitude-control target circuit
101
has the same structure as the delay cells
2
-
6
and the supply voltage VDD is applied to one input terminal (the gate of the NMOS transistor N
6
) of the amplitude-control target circuit
101
while the reference voltage Vref generated by the reference voltage generator
8
is applied to the other input terminal (the gate of the NMOS transistor N
7
). An output voltage from an output terminal
102
of the amplitude-control target circuit
101
on that side where the power supply voltage VDD is input and the reference voltage Vref generated by the reference voltage generator
8
are respectively input to the non-inverting input terminal (+) and the inverting input terminal (−) of the operational amplifier
9
whose output is sent out as the amplitude control voltage Vbp. As this amplitude control voltage Vbp is applied to the gates of the PMOS transistors P
5
and P
6
in the amplitude-control target circuit
101
, feedback control is carried out to make the output voltage from the output terminal
102
equal to the reference voltage Vref generated by the reference voltage generator
8
. This indicates that as the amplitude control voltage Vbp is input to the voltage-controlled oscillation section
100
comprising the delay cells
2
-
6
which have the same circuit structure as that of the amplitude-control target circuit
101
, the output voltage output from the output terminal of the voltage-controlled oscillation section
100
becomes the same as the reference voltage Vref generated by the reference voltage generator
8
when the voltage at one input terminal of each of the delay cells
2
-
6
has the level of the power supply voltage VDD.
Therefore, the amplitude of the oscillation waveform of this voltage-controlled oscillation section
100
is always kept constant by the amplitude control voltage Vbp so that the maximum value of the oscillation waveform becomes the power supply voltage VDD and the minimum value becomes the reference voltage Vref generated by the reference voltage generator
8
.
Further, as the control voltage Vcn which controls the oscillation frequency of the voltage-controlled oscillation section
100
is also input to the amplitude-control target circuit
101
, the amplitude control voltage Vbp changes in accordance with a change in control voltage Vcn. Even if the oscillation frequency of the voltage-controlled oscillation section
100
changes, therefore, the amplitude of the oscillation waveform of the voltage-controlled oscillation section
100
is always kept constant by the amplitude control voltage Vbp so that the maximum value of the oscillation waveform becomes the power supply voltage VDD and the minimum value becomes the reference voltage Vref generated by the reference voltage generator
8
. As a result, the oscillation output as shown in
FIG. 5
is acquired.
FIG. 5
shows the oscillation waveform of the voltage-controlled oscillation section
100
which comprises small-amplitude differential delay cells whose output amplitude is controlled to the level of the power supply voltage VDD from the level of the reference voltage Vref.
As apparent from the above, the small-amplitude outpu
Takada Shuichi
Yoshizawa Akihiko
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Grimm Siegfried H.
Kabushiki Kaisha Toshiba
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