Voltage controlled ring oscillator delay

Details Voltage controlled ring oscillator delay Voltage controlled ring oscillator delay

1999-02-03

2001-04-24

Kinkead, Arnold (Department: 2817)

Oscillators

Ring oscillators

C331S03600C, C331S175000, C327S280000, C327S281000

Reexamination Certificate

active

06222423

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to the field of voltage controlled ring oscillators. More specifically, the invention relates to an improved delay cell within a voltage controlled oscillator which provides a more linear relationship between a control voltage and an output frequency of the oscillator.
BACKGROUND OF THE INVENTION
A voltage controlled ring oscillator includes a number of delay cells n, arranged in a loop. Each cell propagates a clock signal sequentially around the loop and adds delay to the clock signal such that a sum of all the delays represents 360 degrees of phase shift.
FIG. 1
shows a block diagram of a typical voltage controlled ring oscillator
100
. The voltage controlled ring oscillator
100
has an even number of delay cells t
1
-t
4
. Each of these delay cells has a specified timing delay. The delay cells are individually controlled by an incoming voltage control signal V
CONT
. The generation and control of this incoming voltage control signal, V
CONT
is well known in the art. In order to insure that the oscillator forms a clock signal having a 50% duty cycle within the desired frequency range of oscillation, the delay through each of the cells t
1
-t
4
must be uniform. In conventional voltage controlled ring oscillators, the frequency is controlled by varying the delay associated with each delay cell t
1
-t
4
. However, if the frequency does not change in an incremental manner with respect to the control voltage, the result is a non-linear relationship between the input voltage, V
CONT
and the output frequency. This can cause problems when utilizing ring oscillators in phase-locked loops for data recovery.
FIG. 2
illustrates a block diagram of a prior art delay cell
200
within the voltage controlled ring oscillator of FIG.
1
. As shown, an input signal CLKIN is coupled to the first delay element t
1
. The output from the first delay element t
1
, is coupled as an input to two additional delay elements, t
2
and t
3
thereby creating two separate delayed signal pathways. These two delayed signal pathways are each coupled as inputs to a summing junction which, when summed, result in an output signal CLKOUT which is delayed relative to the input signal CLKIN by the overall delay attributable to the individual delay cell within the ring oscillator, which is a weighted sum of each individual delay element within each delay cell comprising the ring oscillator. Generally, the timing delay associated with each delay cell within the voltage controlled ring oscillator must be controlled in order to reach the overall desired oscillation frequency.
One problem with the prior art voltage controlled ring oscillator arrangement is uniform control of each of the two delay pathways within each delay cell. Ideally, it is desired that the output frequency of the ring oscillator increase linearly as the input control voltage is increased. However, voltage drops due to layout, parasitic elements and other problems inherent in the design of the prior art delay cell of
FIG. 2
, result in nonuniform delays from cell to cell. This degrades the linear relationship between the control voltage and the output frequency of the voltage controlled ring oscillator. Accordingly, what is needed is a delay cell for a ring oscillator which provides a more controllable delay path. What is further needed is a ring oscillator having a plurality of delay cells, each having a uniform delay from cell to cell in order to maintain a precise output frequency. What is also needed is a ring oscillator wherein each delay is controlled with uniform delays between each delay cell element.
SUMMARY OF THE INVENTION
A delay cell in a voltage controlled ring oscillator of the present invention uses a two stage delay topology working in concert with a third stage. The third stage is used for amplification and performs a squaring function on the output waveforms to boost the output signal and decrease the rise time of the output signal. The first delay stage in the two stage delay arrangement includes a first pair of transistors with collectors coupled to collector loads, thereby forming a first pair of nodes. In certain circumstances a first and second terminal of a selectable capacitance circuit are also coupled to each of the nodes in the first pair of nodes, with a third terminal of the selectable capacitance circuit coupled to a low voltage supply, Vss to allow a selectable frequency for the ring oscillator. A high voltage supply, FVCC, is also coupled to each of the collector loads. The emitters of each transistor in the first pair of transistors, are coupled together and tied to the low voltage supply, Vss, through a first bias current source. The first bias current source has a constant component and a selectively variable component. In operation, as each transistor in the first pair of transistors is cycled through an activate-deactivate cycle, their collector loads are allowed to charge and discharge, yielding a delayed differential output voltage at the collectors of each transistor in the first pair of transistors due to the finite amount of time required to charge and discharge the collector loads. The total bias current of the first and second stages, along with the collector load resistances at each node in the first pair of nodes, ensure a constant rise and drop in the final signal voltage at the collectors of each transistor.
The first delay stage is coupled to a second delay stage, wherein the differential output voltage from the first delay stage is coupled to the second delay stage. The second stage includes a second pair of transistors with their bases coupled to the differential output voltage from the first delay stage and the collectors of both transistors coupled to the same collector loads of the first delay stage. The emitters of both transistors in the second pair of transistors are coupled together and tied to the low voltage supply Vss through a second bias current source. Unlike the first bias current source, the second bias current source does not have a constant component. Instead, the second bias current source is completely selectively variable. The second stage bias current is inversely related to the selectively variable component of the first stage bias current. A delay associated with the second stage represents a small fraction of the delay attributable to the first stage.
In operation, the output differential voltage at the first delay stage is stable, whereby the collector voltage at one node in the first pair of nodes is higher than the collector voltage at the other node in the first pair of nodes. As the first pair of transistors in the first delay stage are activated, the transistors switch state, such that a conducting transistor ceases to conduct, thereby allowing the voltage at the collector of the transistor to increase. Meanwhile, the nonconducting transistor will begin to conduct, thereby allowing the voltage at the collector to decrease. Accordingly, the two collector voltages of the first pair of transistors in the first delay stage will exponentially rise and fall in opposition such that a previously high voltage node will start to decrease and a previously lower voltage node will begin to increase. As one node voltage increases and the other node voltage decreases, the second pair of transistors in the second delay stage will switch state in the sense that a previously conducting transistor in the second pair will cease to conduct and a previously non-conducting transistor in the second pair will begin to conduct. As the common collector loads are allowed to charge and discharge in this repeatable fashion, the total current flowing through the first delay stage and the second delay stage remains constant, thereby ensuring a constant rise and drop in the voltage level at the common collectors of each transistor.
The invention is an improvement over prior art delay cell designs due to a more linear relationship between the input control voltage and the output frequency. Moreover, because the delay cell of the present in

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