Voltage-controlled osillator

Details Voltage-controlled osillator Voltage-controlled osillator

2005-07-05

2005-07-05

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C375S376000, C331SDIG002

Reexamination Certificate

active

06914465

ABSTRACT:
A PLL circuit that optimally generates a clock signal with two reference signals having different frequencies. The PLL circuit includes a VCO for generating the clock signal in accordance with a control voltage. A first loop controls the frequency of the clock signal in accordance with a first reference signal. A second loop controls the phase of the clock signal in accordance with a second reference signal, whose cycle is longer than that of the first reference signal. The second loop supplies the VCO with the control voltage at a constant value until the difference between the frequencies of the first reference and clock signals converges to within a predetermined range. Then, the second loop supplies the VCO with a control voltage at a level corresponding to the difference between the phases of the second reference and clock signals.

REFERENCES:
patent: 4511859 (1985-04-01), Dombrowski
patent: 5072195 (1991-12-01), Graham et al.
patent: 5088080 (1992-02-01), Ishibashi et al.
patent: 5363419 (1994-11-01), Ho
patent: 5933037 (1999-08-01), Momtaz
patent: 5982208 (1999-11-01), Kokubo et al.
patent: 6215835 (2001-04-01), Kyles

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