Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2000-11-07
2002-05-14
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S00100A, C331S015000, C331S025000, C327S156000, C327S157000, C327S159000
Reexamination Certificate
active
06388531
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of digital phase locked loops, and, more particularly, to a method and device for reducing the level of parasitic lines from an oscillator controlled by a phase locked loop.
BACKGROUND OF THE INVENTION
Phase locked loops (PLL) are used, for example, every time there is a need to create a frequency in an electronic apparatus having a specified value that remains stable over time. Information on the design of such circuits is available in a book by Ulrich L. Rohde titled “Digital PLL Frequency Synthesizers—Theory and Design”, published by Prentice Hall Inc., Englewood Cliffs, N.J., 07632, under reference No. ISBN 0-13 21439-2. Such a device is used to generate a high frequency signal in a precise and controlled manner, such as from 100 MHz to several GHz, for example.
FIG. 1
shows the traditional structure of a digital phase locked loop. A reference signal Fref, generally coming from an oscillator
1
controlled by a quartz crystal
2
, is applied to a phase comparator
3
via a frequency divider
4
. The phase comparator
3
is the heart of the PLL, and controls a voltage controlled oscillator VCO
6
via a loop filter
5
. The signal coming from the VCO
6
is generally applied via a loop divider
7
to the comparator
3
, which sends the signal again around the loop. The signal may be from the VCO
6
or an intermediate signal from the loop divider
7
.
By adjusting the division ranking and the reference and loop dividers, the frequency of the output signal can be changed. The output signal frequency is then fed back to control the reference frequency Fref. The spectral frequency and the stability of the output signal are fixed by the characteristics of the loop and by the performance of the reference signal.
With regard to the traditional structure of the PLL illustrated in
FIG. 1
, particular interest will now be directed to the circuit connected to the output of the phase comparator
3
. Ways of creating a phase comparator circuit are given, for example, in the above referenced book by Rohde, particularly on page 11.
The phase frequency comparator or detector (PFD), which may be called a three state comparator, has one state where the phase of the VCO is delayed with respect to the reference phase, one state where the phase of the VCO is in advance of the reference phase, and another state called the equilibrium state where these phases are in phase or within areas of phase advance or phase delay for which the phase loop is not able to react.
The three state phase frequency comparator has the best performance with respect to capture and linearity, and is the phase comparator that is most often used. This PFD is generally connected to a charge pump
16
whose role is to supply a current related to the relative situation of the inputs to the comparator, Fref and FVCO.
FIG. 2
represents in greater detail the phase comparator
3
and a charge pump circuit
16
connected immediately at an output thereof. The phase comparator
3
includes a first
8
and a second
9
input for receiving respectively the reference frequency Fref and a frequency F
VCO
coming from the VCO. The phase comparator
3
includes two logic outputs
10
,
11
respectively called up and down. These outputs
10
,
11
control current generators
12
,
13
via respective control inputs
14
and
15
.
The current generators
12
,
13
together form the charge pump
16
of the voltage controlled oscillator
6
. The generators
12
,
13
supply current that are in principle equal, but in the opposite direction. Because of the manufacturing tolerances, an imbalance generally exists between the absolute values of the currents supplied by the generators
12
and
13
.
The operation of this circuit will now be explained with reference to
FIGS. 3
to
5
, which represent different signals. The signals represented by lines A and B in
FIG. 3
represent the form of periodic square signals obtained in a known way from frequencies generated by the reference oscillator
1
and the VCO
6
.
In the example shown, for lines A and B the falling edge of the VCO signal is delayed with respect to the rising edge corresponding to the Fref signal, as shown within the ring C. An enlarged view of the temporal relationship between these two edges is shown by lines D and E. The value on the logic outputs
10
and
11
is represented on lines F and G respectively. The charge pump
16
current is shown by line H. This may be a positive current of value +I, a negative current of value −I, or a zero current if neither or both of the two current generators
12
and
13
produce current.
A falling edge for the Fref frequency arriving before the falling edge of the VCO frequency will generate the up output
10
(line F) having logic value 1, for example, commanding generator
12
to supply current. The arrival of the falling edge of the VCO frequency (line E) will generate the output
10
of the comparator
3
having a logic value 0, for example, commanding the generator
12
to switch off. Generator
12
will thus charge the pump for a period of time equal to the phase delay between F
VCO
and Fref. This charging has the effect of bringing the phase delay back to 0.
Referring now to
FIGS. 4 and 5
, what occurs when the frequency F
VCO
is in advance or in phase with respect to the frequency Fref will now be examined. In
FIG. 4
, the falling edge of the signal F
VCO
represented by line E arrives before the falling edge of the signal Fref represented by D. Under these conditions, the operation of the comparator
3
is such that the falling edge of signal F
VCO
will cause a change in the logic value present at output
11
(line G) of the comparator
3
. This value is set at 1, for example.
This output will generate the command
15
for the generator
13
. A current in the opposite direction to that in the preceding case, as mentioned in connection with
FIG. 3
, will be passing through the charge pump
16
. The subsequent arrival of the falling edge of the Fref signal will cause the logic value at output
11
(down) from the comparator
3
to return to the previous logic value 0, for example, which is line G in FIG.
4
. Hence the current flow from generator
13
(line H) is stopped.
In
FIG. 5
, the signals Fref and F
VCO
, i.e., lines D and E are in phase. Under these conditions, the logic values on outputs
10
and
11
, i.e., lines F and G, do not change. The current I, i.e., line H, is zero. The operation which has just been described in connection with
FIGS. 3
to
5
does not discuss reaction times of the phase comparator
3
which will be referred to as Tpfd, and the reaction times of the current generators will be referred to as Tcp. Due to these reaction times there are phase delay and advance areas close to the area referred to as the equilibrium area represented in FIG.
5
. This is where the Fref and F
VCO
phases are in phase, and wherein the comparator
3
and the pump
16
do not have time to react.
In
FIG. 5
, the situation is shown in which the delay of the falling edge of signal F
VCO
is slightly delayed or slightly in advance of the falling edge of the Fref signal and is situated, for example, within the hatched area shown in E in FIG.
5
. This hatched area in
FIG. 5
corresponds to double the minimum time required to start the flow of current from generator
12
or
13
.
Within the time interval represented by the hatched area, the charge pump
16
has not yet reacted to the command provide current when it receives the command to stop providing current. Hence, with regard to the control exerted on the frequency F
VCO
by the phase locked loop, the result illustrated by the curve shown in
FIG. 6
is obtained. This curve shows the output power on the y-axis as a function of the frequency on the x-axis. This curve also shows two plateau areas, substantially symmetrical to one another with respect to an axis YY′, corresponding to the value F
VCO
.
A frequency range marked C, for which the axis YY′ is an axis of symmetry, correspond
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Mis David
STMicroelectronics S.A.
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