Voltage controlled oscillator with frequency stabilized and...

Oscillators – Ring oscillators

Reexamination Certificate

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Details

C331S175000, C331S17700V

Reexamination Certificate

active

06825731

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage controlled oscillator, and more particularly, to a voltage controlled oscillator which can suppress the deviation of an oscillation frequency.
2. Description of the Related Art
A typical voltage controlled oscillator (VCO) generates an output signal oscillating at a frequency determined in accordance with a voltage supplied from an external unit. For example, the voltage controlled oscillator (VCO) is used in various fields such as information processing and communication.
A conventional voltage controlled oscillator (VCO) will be described with reference to FIG.
1
.
FIG. 1
is a circuit diagram showing the circuit structure of the conventional voltage controlled oscillator (VCO). Referring to
FIG. 1
, the conventional voltage controlled oscillator (VCO)
105
is comprised of a bias generator (BG)
108
, a ring oscillator (RO)
109
, and a level converter (L-C)
107
.
A constant voltage V
cnl
with a predetermined voltage value and a control voltage V
cnt
are supplied from an external unit to the bias generator (BG)
108
. Also, a power supply voltage is supplied to the bias generator (BG)
108
and the ring oscillator (RO)
109
from an external unit. The outputs of the bias generator (BG)
108
are supplied to the ring oscillator (RO)
109
. The bias generator (BG)
108
compensates for the operation current of the ring oscillator (RO)
109
. The compensation means to flow the current enough to rapid rising and falling operations of the ring oscillator (RO)
109
. Through this compensation, a high frequency characteristic can be improved. The level converter (L-C)
107
generates an output signal F
VCO
based on the outputs of the ring oscillator (RO)
109
.
The ring oscillator (RO)
109
is comprised of N inversion-type differential amplifier. Here, N is an integer equal to or more than 2. Each of the N inversion-type differential amplifiers operates based on the outputs of the bias generator (BG)
108
. That is, the operation current of each of the N inversion-type differential amplifiers is indirectly determined by the addition of a current I
cnl
determined in accordance with the constant voltage V
cnl
and a current I
cnt
determined in accordance with the control voltage V
cnt
. In this way, in the ring oscillator (RO)
109
, an offset of the oscillation frequency is set based on the constant voltage V
cnl
, and the oscillation frequency is proportional to the voltage V
cnt
. The ring oscillator (RO)
109
supplies one of the maximum voltage V
OUT1
showing the maximum peak and the minimum voltage V
OUT2
showing the minimum peak to the level converter (L-C)
107
through a first output terminal OUT
1
. Also, the ring oscillator (RO)
109
supplies the other of the maximum voltage V
OUT1
and the minimum voltage V
OUT2
to the level converter (L-C)
107
through a second output terminal OUT
2
.
The level converter (L-C)
107
increases voltage difference between the minimum voltage V
OUT2
and the maximum voltage V
OUT1
to a CMOS level and generates the output signal F
VCO
. The output signal F
VCO
generated by the level converter (L-C)
107
is sent out outside as the output signal of the voltage controlled oscillator (VCO)
105
.
A relation of the oscillation frequency of the output signal F
VCO
generated by the voltage controlled oscillator (VCO)
105
and the control voltage V
cnt
will be described.
FIG. 3
is a diagram showing the relation. Referring to
FIG. 3
, when the voltage V
cnt
increases more than a threshold voltage V
a101
of a transistor contained in the voltage controlled oscillator (VCO)
105
, the oscillation frequency of the output signal F
VCO
starts to increase linearly from 0 (Hz), as shown by the symbol X
1
. Thus, the voltage controlled oscillator (VCO)
105
generates the output signal F
VCO
with the oscillation frequency proportional to the control voltage V
cnt
in a range from the threshold voltage V
a101
to the power supply voltage V
DD
. Therefore, when the control voltage V
cnt
is V
b101
(V
a101
<V
b101
<V
DD
), the output signal F
VCO
of a desired oscillation frequency F
b101
can be obtained.
However, the voltage V
b101
receives interference due to a noise component and changes. At that time, the change of the desired oscillation frequency F
b101
becomes large in accordance with the inclination of the frequency characteristic, because the inclination of the frequency characteristic shown by the symbol X
1
is steep. To suppress the large change of the oscillation frequency, an offset frequency F
a101
is presented by the addition of the current I
cnt
corresponding to the constant voltage V
cnt
in the bias generator (BG)
108
. The offset frequency F
a101
is larger than 0 (Hz) and is smaller than the desired frequency F
b101
, and is referred to as a reference frequency or a free-running oscillation frequency. Thus, the voltage controlled oscillator (VCO)
105
can generate the output signal F
VCO
to have frequency characteristic shown by the symbol Y
101
which is more gentle than the frequency characteristic shown by the symbol X
1
.
Next, the bias generator (BG)
108
will be described. The bias generator (BG)
108
is comprised of an addition circuit
108
a
and a mirror circuit
108
b.
The addition circuit
108
a
is comprised of a P-channel MOS (PMOS) transistor
111
, and N-channel MOS (NMOS) transistors
112
and
113
. The higher side power supply voltage V
DD
is connected with the source electrode of the PMOS transistor
111
. The drain electrode of the PMOS transistor
111
is connected with the drain electrodes of the NMOS transistors
112
and
113
. The constant voltage V
cnl
is supplied to the gate electrode of the NMOS transistor
112
from the external unit. Also, the source electrode of the NMOS transistor
112
is connected with the lower power supply voltage, and generally is grounded. The voltage V
cnt
is supplied to the gate electrode of the NMOS transistor
113
from the external unit. Also, the source electrode of the NMOS transistor
113
is connected with the lower power supply voltage, and generally is grounded.
The mirror circuit
108
b
is comprised of a PMOS transistor
114
and an NMOS transistor
115
. The higher power supply voltage V
DD
is connected with the source electrode of the PMOS transistor
114
. The gate electrode of the PMOS transistor
114
is connected with the drain electrode of the PMOS transistor
111
. The drain electrode of the NMOS transistor
115
is connected with the drain electrode of the PMOS transistor
114
. Also, the source electrode of the NMOS transistor
115
is connected with the lower power supply voltage, and generally is grounded.
The mirror circuit flows through a second transistor connected with a first transistor, the current with the same value as the value of current which flows through the first transistor or a value proportional to the value of current which flows through the first transistor like a mirror. The current which flows through the second transistor increases proportionally, if the current which flows through the first transistor increases. Therefore, the output of the PMOS transistor
111
is supplied from the bias generator (BG)
108
to the ring oscillator (RO)
109
as a signal corresponding to an addition of the current I
cnl
determined in accordance with the constant voltage V
cnl
and the current I
cnt
determined in accordance with the voltage V
cnt
. Also, the output of the PMOS transistor
114
is supplied from the bias generator (BG)
108
to the ring oscillator (RO)
109
.
Next, the ring oscillator (RO)
109
will be described. In the conventional voltage controlled oscillator shown in
FIG. 1
, the above-mentioned N is an even number equal to or more than 2, and specifically N is 4. In this case, the ring oscillator (RO)
109
is comprised of first to fourth inversion-type differential amplifiers
109
a
,
109
b
,
109
c,
and
109
d.
Each of the first to fourth inversion-type differential amplifiers
109
a
,

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