Voltage controlled oscillator with delay circuits

Details Voltage controlled oscillator with delay circuits Voltage controlled oscillator with delay circuits

2001-01-25

2002-10-29

Kinkead, Arnold (Department: 2817)

Oscillators

Ring oscillators

C331S17700V, C331S175000, C327S266000, C327S274000

Reexamination Certificate

active

06472944

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage-controlled oscillator (VCO), and particularly to a ring VCO that is constituted by MOS (Metal-Oxide Semiconductor) transistors and that features stable operation and a broad variable frequency range.
2. Description of the Related Art
A VCO is a crucial circuit for determining the characteristics of a PLL (Phase-Locked Loop). A desirable VCO offers continuous frequency change over a broad frequency band, realizes stable oscillation, and has low noise characteristics.
A ring VCO is typically used in cases in which a VCO is to be integrated in LSI (Large-Scale Integration) such as in an ASIC (Application-Specific Integrated Circuits), because this VCO can be constructed without using inductors or capacitors, and further, the VCO allows the use of differential circuits, which are not vulnerable to noise from the power supply. A circuit described in the paper “An Integrable 1-2.5 Gbps Low-Jitter CMOS Transceiver with Built-In Self-Test Capability” (1999 Symposium on VLSI Circuits Digest of Technical Papers
5-2
) is typically used as the differential circuit that is used in this type of ring VCO.
Referring now to
FIG. 1
, a block diagram is shown of the overall construction of one example of a ring VCO of the prior art that is made up of a plurality of gate circuits. In this figure, the internal constructions of basic cells
100
-
1
to
100
-N are all identical, and the internal construction of basic cell
100
-
1
is shown in
FIG. 2
as representative of these basic cells
100
-
1
to
100
-N.
The conventional VCO shown in
FIG. 1
is made up of N basic cells
100
-
1
to
100
-N (N≧1) connected in a series. Basic cells
100
-
1
to
100
-N are each provided with: two cell input terminals IN
1
and IN
2
; two cell output terminals OUT
1
and OUT
2
from which signals that have been received via cell input terminals IN
1
and IN
2
are outputted in non-inverted form; and two control terminals E and F for receiving signals for controlling the currents that flow through each of basic cells
100
-
1
to
100
-N.
Each of basic cells
100
-
1
to
100
-N are connected in an order such that signals outputted from cell output terminals OUT
1
and OUT
2
of a preceding-stage basic cell are applied to cell input terminals IN
1
and IN
2
, respectively, of the next-stage basic cell. In addition, output terminals OUT
1
and OUT
2
of last-stage basic cell
100
-N are connected to feed back to input terminals IN
2
and IN
1
, respectively, of first-stage basic cell
100
-
1
such that the logic is inverted, thereby realizing the oscillation operation.
Referring now to
FIG. 2
, the construction of basic cells
100
-
1
to
100
-N is next explained with basic cell
100
-
1
as an example.
Basic cell
100
-
1
is made up of NMOS (n-channel MOS) transistors M
101
, M
102
, and M
105
; and PMOS (p-channel MOS) transistors M
103
and M
104
. NMOS transistor M
101
and PMOS transistor M
103
form one set and NMOS transistor M
102
and PMOS transistor M
104
form another set, these sets constituting a differential circuit in which these set make a pair. The drains of PMOS transistors M
103
and M
104
are connected to power-supply voltage line V
1
in common, the gates of these transistors are connected to control terminal F in common, and the sources of these transistors are connected to the drains of NMOS transistors M
101
and M
102
, respectively. NMOS transistors M
101
and M
102
have their gates connected to cell input terminals IN
1
and IN
2
, respectively, of basic cell
100
-
1
, and their sources connected to the drain of NMOS transistor M
105
in common. In addition, NMOS transistor M
105
has its gate connected to control terminal E of basic cell
100
-
1
, and its source connected to power supply voltage V
2
. The logic of output terminals OUT
1
and OUT
2
is thus inverted with each other to become the differential output.
Next, regarding the operation of the ring VCO that is constructed according to the foregoing explanation.
In basic cell
100
-
1
, the differential signals that are applied to cell input terminals IN
1
and IN
2
are outputted as non-inverted signals from cell output terminals OUT
1
and OUT
2
with a prescribed delay time. The signals that are outputted from cell output terminals OUT
1
and OUT
2
of basic cell
100
-
1
are applied to cell input terminals IN
1
and IN
2
of basic cell
100
-
2
, and similarly outputted as non-inverted signals from cell output terminals OUT
1
and OUT
2
of basic cell
100
-
2
with a prescribed delay time. Similarly, signals that are outputted from cell output terminals OUT
1
and OUT
2
of a preceding-stage basic cell are successively applied to cell input terminals IN
1
and IN
2
of the next-stage basic cell up to last-stage basic cell
100
-N.
The signals that are outputted from cell output terminals OUT
1
and OUT
2
of last-stage basic cell
100
-N are applied to cell input terminals IN
2
and IN
1
, respectively, of first-stage basic cell
100
-
1
such that the logic of the signals is reversed, i.e., such that the differential logic value are inverted. The oscillation operation is thus obtained by successively applying differential signals that are inputted to basic cell
100
-
1
to basic cells
100
-
2
through
100
-N, and then applying the differential signals that are outputted from basic cell
100
-N to basic cell
100
-
1
.
In this case, the oscillation frequency of the ring VCO is determined by the sum delay time of the number of connected stages of basic cells, with the delay time in each basic cell as a standard.
Furthermore, the current flowing to NMOS transistor M
105
is determined by the internal resistances of PMOS transistors M
103
and M
104
that are regulated based on signals applied to control terminal F, and by signals applied to control terminal E. The delay in each basic cell is determined by the current that flows through this NMOS transistor M
105
. A desired oscillation frequency can therefore be obtained by using a PLL to control the voltage applied to control terminal E.
Nevertheless, the ring VCO according to the above description has the following problems:
(1) In order to vary the delay time in a basic cell, the internal resistance of PMOS transistors is regulated by means of the control voltage applied to the gate of the PMOS transistors or the current flowing to the basic cells is regulated by means of the control voltage applied to the gates of the NMOS transistors; but since the output amplitude also fluctuates in accordance with this current, there is a possibility danger that the oscillation will be halted depending on the combination of the operating current and the control voltage applied to the PMOS transistors.
(2) Both fluctuation in the power supply voltage and the noise that is generated from the circuit for outputting control signals for regulating the load resistance may cause the voltage across the gate and source of the PMOS transistors for adjusting load to fluctuate, and this tends to cause jitter.
(3) Regarding the characteristics of PMOS transistors, discrepancies that tend to occur in the fabrication process may give rise to variation in the internal resistance that corresponds to the control voltage that is applied to the PMOS transistors. Variation therefore occurs in the load resistance of the basic cells, and this variation complicates the accurate adjustment of delay time in the basic cells.
SUMMARY OF THE INVENTION
The present invention was realized in view of the problems of the prior art described hereinabove, and has as an object the provision of a voltage controlled oscillator (VCO) that is capable of a uniform output amplitude, that has minimal jitter, and that has a stable and broad variable frequency range.
The object of the present invention is achieved by a voltage-controlled oscillator that comprises:
a plurality of basic cells; and
a center frequency adjustment circuit that outputs a control signal for setting a delay time for each of the plurality of

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