Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2002-03-13
2004-08-03
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S266000, C327S280000, C331S057000
Reexamination Certificate
active
06771105
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to voltage controlled oscillator (“VCO”) circuits, and more particularly to voltage controlled oscillator circuits that can be programmed to operate in any of several frequency ranges over a very wide band of such frequency ranges.
Phase locked loop (“PLL”) circuitry is frequently used for such purposes as helping to retrieve data from a signal that may vary in frequency and/or phase. The PLL may be in relatively general-purpose circuitry such as a programmable logic device (“PLD”) that may need to support signaling at any frequency in a wide range of frequencies. (For examples of PLDs employing PLLs, see Aung et al. U.S. patent application Ser. No. 09/805,843, filed Mar. 13, 2001.) The range of frequencies over which a PLL may be required to operate is steadily increasing, particularly at the upper end (i.e., higher frequencies). At the same time, power supply voltages for integrated circuits are decreasing, making it more difficult to extend the operating range of PLL circuits.
SUMMARY OF THE INVENTION
A delay cell (e.g., for use in the voltage controlled oscillator (“VCO”) of a PLL) includes a plurality of load resistance transistors connectable in parallel with one another, a plurality of bias current transistors connectable in parallel with one another, and a switching transistor connected in series between the load resistance transistors and the bias current transistors. Switching circuitry allows the number of the load resistance transistors that are actually operating in parallel to be selected. Other switching circuitry similarly allows the number of the bias current transistors that are actually operating in parallel to be similarly selected. This ability to essentially reconfigure the delay cell allows the operating range (i.e., the time delay characteristic) of the delay cell to be greatly extended. A VCO may include a plurality of such delay cells connected in a closed loop series. The extended operating range of the delay cells similarly greatly extends the operating frequency range of a VCO made up of such cells. The same is true for the operating range of a PLL that includes such a VCO.
The delay cell may be differential in construction and operation.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.
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U.S. patent application Ser. No. 09/805,843, Aung et al., filed Mar. 13, 2001.
“ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC”, Preliminary Data Sheet, Jul. 2001, Agere Systems Inc., pp. 1-35.
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Andrasic Stjepan William
Lee Chong H.
Patel Rakesh H.
Aldridge Jeffrey C.
Altera Corporation
Fish & Neave
Jackson Robert R.
Lam Tuan T.
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