Oscillators – Ring oscillators
Reexamination Certificate
1996-09-05
2002-07-02
Mis, David (Department: 2817)
Oscillators
Ring oscillators
C331S074000, C331S17700V, C331S185000
Reexamination Certificate
active
06414556
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage controlled oscillator, and more specifically to a voltage controlled oscillator having an oscillation frequency variation minimized in comparison with a power supply voltage variation.
2. Description of Related Art
For example, Ian A. Young et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, IEEE Journal of Solid State Circuits, Vol. 27, No. 11, pp.1599-1607, November 1992, proposes one prior art voltage controlled oscillator, the disclosure of which is incorporated by reference in its entirety into this application.
Referring to
FIG. 1
, there is shown a circuit diagram of one example of the prior art voltage controlled oscillator based on the above quoted paper. This prior art voltage controlled oscillator includes a ring oscillator constituted of a plurality of differential amplifier type delay circuits
912
which are connected in cascade to form a closed ring by feeding back an output of a last stage delay circuit to an input of a first stage delay circuit, a dummy bias circuit
911
and a voltage-to-current converter
910
, coupled as shown.
Each of the delay circuits
912
includes a pair of pMOS transistors MP
101
and MP
102
having their sources common-connected to each other o form a differential pair, a constant current source pMOS transistor MP
103
connected between a first power supply voltage terminal
920
and the common-connected sources of the pMOS transistors MP
101
and MP
102
, and a pair of voltage controlled resistors
901
connected, as a load, between a drain of the pMOS transistors MP
101
and MP
102
and a second power supply voltage terminal
921
, respectively. Here, the voltage controlled resistor means a resistor having its resistance value which can be controlled by the magnitude of an applied voltage. A low level of an output of each delay circuit
912
(namely, an output of the oscillator) is at a potential level of the second power supply voltage terminal
921
. Assuming that a current value of the associated constant current source MP
103
is “I” and a resistance value of the associated voltage controlled resistors
901
is “R”, a high level of the output of each delay circuit
912
is a potential level which is higher than the potential level of the second power supply voltage terminal
921
, by a voltage of “R·I”.
Furthermore, an input-to-output delay time of each delay circuit
912
is determined by both of a potential difference between a potential level of a current control signal line
930
and a potential level of the first power supply voltage terminal
920
, and a potential difference between a potential level of a voltage control signal line
931
and a potential level of the second power supply voltage terminal
921
. Namely, the input-to-output delay time is determined by a gate-source voltage of the constant current source pMOS transistor MP
103
(constant current value) and the resistance value of the voltage controlled resistors
901
functioning as a load resistor.
In addition, an oscillation frequency of the signal obtained from an output terminal
922
is determined by a potential difference between a potential level on a control terminal
923
of the voltage-to-current converter
910
and the potential level of the second power supply voltage
921
, by action of the voltage-to-current converter
910
.
The dummy bias circuit
911
operates to determine a potential level of the voltage control signal line
931
to the effect that the signal obtained from an output terminal
922
assumes a high level equal to a potential level given to an amplitude control terminal
924
and a low level equal to the potential level of the second power supply voltage
921
.
In brief, the dummy bias circuit
911
comprises, similarly to the delay circuit
912
, a constant current source pMOS transistor MP
103
, a differential transistor pair consisting of a pair of pMOS transistors MP
101
and MP
102
, and a pair of voltage controlled resistors
901
functioning as a load resistor. The dummy bias circuit
911
further includes an operational amplifier OP
1
having an inverting input connected to the amplitude control terminal
924
and a non-inverting input connected to a connection node N
1
between one transistor MP
102
of the differential transistor pair and the associated voltage controlled resistor
901
. An output of the operational amplifier OP
1
is applied to a control input of the voltage controlled resistors
901
in the dummy bias circuit
911
, thereby to make a potential of the node N
1
equal to a high level reference voltage applied to the amplitude control terminal
924
. Furthermore, the output of the operational amplifier OP
1
is applied through the current control signal line
931
to a control input of all the voltage controlled resistors
901
of the delay circuits
901
, so that the high level of the signal obtained from an output terminal
922
becomes equal to the high level reference voltage given to an amplitude control terminal
924
.
With the above mentioned arrangement, even if the current value of the constant current source in each delay circuit
912
is caused to change (namely, the oscillation frequency is changed), the amplitude of the signal obtained from an output terminal
922
is maintained at a constant magnitude.
In the above mentioned prior art voltage controlled oscillator, in ordinary cases, the potential level of the signal supplied to the control terminal
923
varies or fluctuates in phase with the voltage level of the second power supply voltage terminal
921
. Therefore, even if the voltage level of the second power supply voltage terminal
921
varies or fluctuates, the oscillation frequency of the signal obtained from the output terminal
922
is subjected to almost no influence.
However, when the voltage level of the first power supply voltage terminal
920
varies or fluctuates, the voltage-to-current converter
910
controls the potential level of the current control signal line
930
in order to avoid variation of the input-to-output delay time of each delay circuit
912
. However, if the frequency of the variation or fluctuation of the voltage level of the first power supply voltage terminal
920
becomes as high as the voltage-to-current converter
910
cannot follow the voltage level variation or fluctuation, the input-to-output delay time of each delay circuit
912
changes, with the result that the oscillation frequency of the signal obtained from the output terminal
922
changes. As a result, for example, it is not possible to cope with a temporary voltage drop within a LSI (large scaled integrated circuit) chip caused because a current starts or stops flowing when a part of circuits in the LSI chip starts or stop operating.
Here, the frequency of the voltage level variation or fluctuation which the voltage-to-current converter
910
cannot follow, is determined by a parasitic capacitance of the current control signal line
930
, a gate capacitance of the pMOS transistors having a gate connected to the current control signal line
930
, and the characteristics of a pMOS transistor which constitutes the current control signal line
930
.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a voltage controlled oscillator which has overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a voltage controlled oscillator having an oscillation frequency variation minimized in comparison with a power supply voltage variation.
The above and other objects of the present invention are achieved in accordance with the present invention by a voltage controlled oscillator including:
an oscillator connected between a high potential power supply line and a low potential power supply line, for generating an oscillation signal having a frequency changing dependently upon a voltage difference between the high potential power supply line and the low potential power supply line
Dickstein , Shapiro, Morin & Oshinsky, LLP
Mis David
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