Oscillators – Ring oscillators
Reexamination Certificate
1999-02-26
2001-02-06
Kinkead, Arnold (Department: 2817)
Oscillators
Ring oscillators
C331S00100A, C331S045000, C331S049000, C331S074000, C327S159000
Reexamination Certificate
active
06184754
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a voltage-controlled oscillator circuit and a voltage-controlled oscillating method, capable of changing an oscillating frequency in response to an externally supplied control voltage. More specifically, the present invention is directed to a technique suitable for realizing a voltage-controlled oscillator circuit by employing a phase-locked loop (PLL) circuit.
2. Description of the Related Art
Conventionally, this sort of voltage-controlled oscillator circuit is known as, for instance, a circuit shown in FIG.
1
. This conventional voltage-controlled oscillator circuit is described more in detailed, for example, in “3 GHz GaAs PLL clock pulse generator” written by T. OKUYAMA and T. ENOMOTO, Shingaku-Giho No. ED93-152 published by the institute of Electronics, Information and Communication Engineers in JAPAN.
As indicated in
FIG. 1
, the conventional voltage-controlled oscillator circuit has inverters
101
1
to
101
3
. These inverters
101
1
to
101
3
invert a polarity of a signal entered from an input terminal T
I
, and output the polarity-inverted signal from an output terminal T
O
. In general, such a circuit is referred to as a “ring oscillator”. This ring oscillator is constituted by connecting the odd number (three inverters in
FIG. 1
) of inverters in a ring shape.
That is, the first inverter
101
1
is constituted by an enhancement-mode field-effect transistor (E-FET) QE
1
, a first depletion-mode field-effect transistor (D-FET) QD
1
, and a second depletion-mode field-effect transistor QD
2
. A source electrode S of the E-FET QE
1
is connected to the ground potential, and a gate electrode G thereof is connected to the input terminal T
I
. A gate electrode G of the first D-FET QD
1
is connected to a drain electrode of the E-FET QE
1
, and a source electrode S of this first D-FET QD
1
is connected to this drain electrode of the E-FET QE
1
, and also a drain electrode D thereof is connected to a power supply Vd. A source electrode S of the second D-FET QD
2
is connected to the drain electrode D of the E-FET QE
1
, and a drain electrode D of this second D-FET QD
2
is connected to the power supply Vd. Both a drain electrode D of the E-FET QE
1
and a source electrode S of the first D-FET QD
1
are connected to the output terminal T
O
, and a gate electrode G of the second D-FET QD
2
is connected to a voltage control terminal Tc. A control voltage Vc used to vary an oscillating frequency is applied to this voltage control terminal Tc. It should be noted that the structures of the inverters
101
2
and
101
3
are identical to the structure of the above-explained inverter
101
1
.
In this ring oscillator circuit arrangement, the E-FET QE
1
among the respective structural elements of the inverter
101
1
is operable as a driver circuit for driving the next-staged inverter
101
2
, and the first D-FET QD
1
constitutes a load of this E-FET QE
1
. The load current flowing through the inverter
101
1
may be controlled by connecting the second D-FET QD
2
in parallel to this load transistor, namely the first D-FET QD
1
. In this inverter
101
1
, a current established by summing a constant current flowing through QD
1
with a variable current (variable by control voltage V
c
) flowing through QD
2
will flow. This summed current may determine the propagation delay time “tpd” of the inverter
101
. Both the inverter
1012
and the inverter
101
3
are operable in a similar manner to that of the above-explained inverter
101
1
.
Since the oscillating frequency of the voltage-controlled oscillator circuit is varied in response to the propagation delay time of the overall circuit arrangement, this oscillating frequency can be controlled based upon the control voltage V
c
. For instance, when the current flowing through the second D-FET QD
2
is decreased by lowering this control voltage V
c
, the pull-up ability of QD
2
with respect to the power supply Vd is weakened. As a result, the propagation delay time tpd of each of the inverters is increased, so that the oscillating frequency of the voltage-controlled oscillator circuit is lowered. Conversely, when the current flowing through the second D-FET QD
2
is increased by increasing the control voltage V
c
, the pull-up ability thereof with respect to the power supply Vd is strengthened. As a result, the propagation delay time tpd of each of the inverters is decreased, so that the oscillating frequency of the voltage-controlled oscillator circuit is increased.
FIG. 2
is a diagram for showing a relationship of the oscillating frequency with respect to the threshold voltage Vt of the D-FET used in a voltage-controlled oscillator circuit similar to the voltage controlled oscillator circuit indicated in
FIG. 1
, namely a graphic representation for indicating a permitted variation range of the threshold voltage Vt by which the conventional oscillator circuit can be oscillated at various frequencies. An abscissa of the graphic representation shown in
FIG. 2
indicates a threshold voltage [V] of the D-FET, whereas an ordinate thereof represents an oscillating frequency [GHz] (VCO oscillating frequency) of this voltage-controlled oscillator circuit. In other words,
FIG. 2
represents a simulation result of a permitted variation range for various threshold voltages at which the conventional voltage-controlled oscillator can be oscillated in various frequencies, while varying the control voltage from 0.1V to 0.8V. In this simulation, as with this conventional voltage-controlled oscillator circuit, a ring oscillator arranged by 9 sets of inverters with employment of GaAs D-FETs and GaAs E-FETs is employed. Also, the power supply voltage is selected to be 2[V].
As indicated in
FIG. 2
, in the case that the conventional voltage-controlled oscillator circuit is oscillated at the frequency of 1[GHz], the permitted variable range of the threshold voltage Vt of the D-FET is defined from −0.70[V] to −0.30[V], namely 0.40[V].
There are some possibilities that the threshold voltage Vt of the D-FET is shifted, or deviated from the designed value, because of fluctuations occuring when this D-FET is manufactured. In this case, while the gate-to-source voltage V
gs
of the first D-FET QD
1
which constitutes the inverter is a constant voltage (=0[V]), since the value of the current flowing through the first D-FET QD
1
is varied, the oscillating frequency is shifted from a desirable frequency.
A voltage-controlled oscillator circuit is mainly employed in a loop of a PLL circuit, and is required to be oscillated at a preselected frequency (for example, 1[GHz]) in response to an input voltage. However, there is a certain possibility that when the above-explained voltage-controlled oscillator circuit is employed in a PLL circuit, since the permitted variation range of the threshold voltage Vt of the D-FET is narrow, this voltage-controlled oscillator cannot be oscillated under stable condition.
As the related art, for instance, Japanese Laid-open Patent Disclosure (JP-A-Heisei 6-334515) discloses “PHASE-SYNCHRONIZED OSCILLATOR CIRCUIT”. In this phase-synchronized oscillator circuit, a ring oscillator is arranged by the first to fifth inverter chains, the basic inverter chain, and the first to fifth selectors. In the first to fifth inverter chains, 2 sets of inverters; 4 sets of inverters; 8 sets of inverters; 16 sets of inverters; and 32 sets of inverters are series-connected to each other respectively. In the basic inverter chain, the even numbers of inverters are series-connected to each other. The first to fifth selectors control whether or not each of these first to fifth inverter chains is engaged into the loop. Also, this phase-synchronized oscillator circuit is arranged by the phase comparing circuit, and the up/down counter. The phase comparing circuit compares the phase of the input clock signal with the phase of the oscillator c
Kinkead Arnold
NEC Corporation
Young & Thompson
LandOfFree
Voltage-controlled oscillator circuit and voltage-controlled... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Voltage-controlled oscillator circuit and voltage-controlled..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage-controlled oscillator circuit and voltage-controlled... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2579619