Oscillators – With particular source of power or bias voltage
Reexamination Certificate
2002-04-15
2004-08-17
Pascal, Robert (Department: 2817)
Oscillators
With particular source of power or bias voltage
C331S002000, C331S158000, C714S815000
Reexamination Certificate
active
06778032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage controlled oscillator capable of changing an oscillation frequency by voltage control and a phase-locked oscillator using the same.
2. Description of the Background Art
Conventionally, phase-locked oscillators (PLOs) using voltage controlled oscillators have been used as microwave oscillators for oscillating at microwave frequencies.
FIG. 17
is a block diagram showing an example of the configuration of a conventional frequency division type phase-locked oscillator.
In
FIG. 17
, the phase-locked oscillator comprises a reference signal source
2
, a phase comparator
3
, a low-pass filter
4
, a voltage controlled oscillator (hereinafter referred to as VCO)
10
, a power distributor
9
, and a frequency divider
5
.
The reference signal source
2
generates a reference signal. The phase comparator
3
compares the phase of the reference signal generated by the reference signal source
2
with the phase of a frequency division signal fed from the frequency divider
5
, described later, and outputs a phase difference signal corresponding to a phase difference between the signals. The low-pass filter
4
passes a low frequency component of the phase difference signal outputted from the phase comparator
3
, and feeds the low frequency component to a control terminal
111
of the VCO
10
as a control voltage Vc.
The VCO
10
outputs to an output terminal
112
an output signal Out having a frequency corresponding to the control voltage Vc at the control terminal
111
. The output signal Out at the output terminal
112
of the VCO
10
is outputted to an output terminal
16
by the power distributor
9
, and is fed to the frequency divider
5
as a feedback signal. The frequency divider
5
frequency-divides the feedback signal fed from the power distributor
9
, and feeds the feedback signal to the phase comparator
3
as a frequency division signal. In such a way, a phase-locked loop is configured.
FIG. 18
is a block diagram showing an example of the configuration of a conventional sampling type phase-locked oscillator.
In
FIG. 18
, the phase-locked oscillator comprises a reference signal source
2
, a sampling phase detector (hereinafter referred to as SPD)
6
, a low-pass filter
4
, a VCO
10
, and a power distributor
9
.
The reference signal source
2
generates a reference signal. The SPD converts the reference signal generated by the reference signal source
2
into a pulse train, samples a feedback signal fed from the power distributor
9
, described later, using the pulse train, to detect a relative phase difference between the reference signal and the feedback signal, and feeds a phase difference signal to the low-pass filter
4
. The low-pass filter
4
passes a low frequency component of the phase difference signal fed from the SPD
6
, and feeds the low frequency component to a control terminal
111
of the VCO
10
as a control voltage Vc.
The VCO
10
outputs to an output terminal
112
an output signal Out having a frequency corresponding to the control voltage Vc at the control terminal
111
. The output signal Out at the output terminal
112
of the VCO
10
is outputted to an output terminal
16
by the power distributor
9
, and is fed to the SPD
6
as a feedback signal. In such a way, a phase-locked loop is configured.
In each of the phase-locked oscillators shown in
FIGS. 17 and 18
, when a load connected to the output terminal
16
varies, an oscillation frequency is changed. Therefore, JP-A-60-53306, for example, has proposed that in order to stabilize the oscillation frequency against the variation in the load, an output circuit composed of an attenuator, a buffer amplifier, an isolator, or the like is added to an oscillation circuit in the VCO, to separate the VCO and the load.
FIG. 19
is a block diagram showing the configuration of the VCO
10
in each of the phase-locked oscillators shown in
FIGS. 17 and 18
.
The VCO
10
comprises an oscillation circuit
100
and an output circuit
110
. The output circuit
110
is composed of an attenuator, a buffer amplifier, an isolator, or the like. A control voltage Vc is fed to the control terminal
111
of the oscillation circuit
100
. A power supply voltage Vdd is fed to a power supply terminal
114
of the oscillation circuit
100
by a DC power supply. Further, the oscillation circuit
100
is connected to the output terminal
112
through the output terminal
110
composed of an attenuator or the like.
In the conventional VCO
10
, the output circuit
110
is thus inserted between the oscillation circuit
100
and the output terminal
112
, thereby making it possible to stabilize the oscillation frequency against the variation in the load.
In the above-mentioned conventional phase-locked oscillator, the output circuit
110
is inserted between the oscillation circuit
100
in the VCO
10
and the output terminal
112
. Accordingly, the output power of the oscillation circuit
100
is attenuated by passing through the output circuit
110
. Consequently, the power of the feedback signal returned to the frequency divider
5
or the SPD
6
is attenuated. In order to obtain a feedback signal having predetermined power, therefore, the output power of the oscillation circuit
100
must be increased in consideration of the amount of attenuation by the output circuit
110
. As a result, power consumption is increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a voltage controlled oscillator capable of reducing the output power of an oscillation circuit while stabilizing an oscillation frequency against the variation in a load and a phase-locked oscillator using the same.
A voltage controlled oscillator according to an aspect of the present invention comprises a control terminal receiving a control voltage; an output terminal; a feedback terminal; an oscillation circuit that generates a signal having a frequency corresponding to the control voltage at the control terminal; a power supply terminal for applying a power supply voltage to the oscillation circuit; an output circuit that outputs to the output terminal the signal generated by the oscillation circuit; and a distribution circuit that distributes a part of the signal generated by the oscillation circuit to the feedback terminal as a feedback signal.
In the voltage controlled oscillator according to the present invention, the signal having the frequency corresponding to the control voltage at the control terminal is generated by the oscillation circuit, and is outputted to the output terminal by the output circuit. In this case, the output circuit is inserted between the oscillation circuit and the output terminal. Therefore, the oscillation frequency of the oscillation circuit is prevented from being changed by the variation in a load connected to the output terminal.
Furthermore, a part of the signal generated by the oscillation circuit is distributed to the feedback terminal as the feedback signal, whereby the feedback signal is not attenuated by the output circuit. Consequently, it is possible to reduce the output power of the oscillation circuit which is required to obtain the feedback signal having predetermined power.
Consequently, it is possible to reduce the output power of the oscillation circuit while stabilizing the oscillation frequency against the variation in the load.
In the voltage controlled oscillator, the distribution circuit may comprise a branch circuit that leads to the feedback terminal a signal leaking out to the power supply terminal from the oscillation circuit.
In this case, the signal leaking out to the power supply terminal from the oscillation circuit is used as the feedback signal. Consequently, the feedback signal is not attenuated by the output terminal.
The branch circuit may comprise a capacitor and an amplifier which are connected in series between the power supply terminal and the feedback terminal.
In this case, the passage of a DC component is rejected by the capacitor, and the signal
Armstrong Kratz Quintos Hanson & Brooks, LLP
Chang Joseph
Pascal Robert
Sanyo Electric Co,. Ltd.
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