Voltage controlled oscillator

Details Voltage controlled oscillator Voltage controlled oscillator

2005-05-03

2005-05-03

Mis, David (Department: 2817)

Oscillators

Combined with particular output coupling network

Space discharge or unilaterally conductive device in output...

C331S057000, C331S074000, C330S252000, C330S253000, C375S376000

Reexamination Certificate

active

06888417

ABSTRACT:
A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

REFERENCES:
patent: 5966030 (1999-10-01), Schmitt et al.
Lee, C. Yoo, W. Kim, S. Chai, and W. Song, “A 622Mb/s CMOS Clock Recovery PLL with Time-Interleaved Phas Detector Array,” inIEEE ISSCC Dig. Tech Papers, Feb. 1996, pp. 198-199.
Fiedler, R. Mactaggart, J. Welch, and S. Krishnan, “A 1.0625 Gbps Transceiver with 2×-Oversampling and Transmit Signal Pre-Emphasis,” inIEEE ISSC Dig. Tech. Papers, Feb. 1997, pp. 238-239.
R. Gu, J. M. Tran, H.-C. Lin, A.-L. Yee, and M. Izzard, “A 0.5-3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transceiver,” inIEEE ISSCC Dig. Tech. Papers, Feb. 1999, pp. 352-353.
T. H. Lee, K. S. Donnelly, J. T. C. Ho, J. Zerbe, M. G. Johnson, and T. Ishikawa, “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,”IEEE J. Solid-State Circuits, vol. 29 (Dec. 1994), pp. 1491-1496.
Efendovich, Y. Afek, C. Sella, and Z Bikowsky, “Multifrequency Zero-Jitter Delay-Locked Loop,”IEEE J. Solid-State Circuits, vol. 29, No. 1 (Jan. 1994), pp. 26-70.
S. Sidiropoulos, and M. A. Horowitz, “A Semi-Digital Dual Delay-Locked Loop,”IEEE J. Solid-State Circuits, vol. 32, No. 11, (Nov. 1997), pp. 1683-1692.
Y. Moon, J. Choi, K. Lee, D.-K. Jeong, and M.-K Kim, “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance,”IEEE J. Solid-State Circuits, vol. 35, (Mar. 2000), pp. 377-384.
Ian A. Young, J. K. Greason, and K. L. Wong, “A PLL Clock generator with 5 to 100 MHz of Lock Range for Microprocessors”,IEEE Journal of Solid-State Circuits, vol. SC-27, (Nov. 1992), pp. 1599-1607.

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