Voltage-controlled oscillator

Oscillators – Ring oscillators

Reexamination Certificate

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Details

C327S103000

Reexamination Certificate

active

06229403

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage-controlled oscillator which has excellent input and output characteristics that do not depend upon fluctuations or variations in the power supply voltage, temperature, manufacturing process and others, and which provides a high oscillation frequency.
2. Prior Art
Various types of voltage-controlled oscillators (VCO) are known which are adapted to oscillate at an oscillation frequency that varies with input voltage. Among these, ring oscillator type VCO is constructed such that a plurality of inverters are connected in a ring-like arrangement, and thus favorably used in digital circuits.
FIG. 1
shows the configuration of a known voltage-controlled oscillator. The voltage-controlled oscillator VCO is principally comprised of a V-I converter
1
and a ring oscillator
2
, and has a control input terminal CONT to which a control signal CS is supplied.
The V-I converter
1
serves to convert the voltage level Vin of the control signal CS into a corresponding current value. As shown in
FIG. 1
, the V-I converter
1
includes an op amp (operational amplifier) OP, a p-channel transistor P
1
, a resistance R connected in series with the p-channel transistor P
1
, a p-channel transistor P
2
, and an n-channel transistor N
1
connected in series with the p-channel transistor P
2
. The gate of the p-channel transistor P
1
is connected to the output terminal of the op amp OP, and the drain of the same transistor P
1
is connected to the positive input terminal of the op amp OP. The gates of the p-channel transistors P
1
, P
2
are connected to each other (namely, the p-channel transistors P
1
, P
2
have a common gate), so that the p-channel transistor P
2
forms a current mirror circuit with the p-channel transistor P
1
. The gate and drain of the n-channel transistor N
1
are connected to each other, namely, the n-channel transistor N
1
is of diode-connected type. With this arrangement, the drain voltage Vr of the p-channel transistor P
1
is applied to the positive input terminal of the op amp OP in a feedback manner, so that the voltage Vr is controlled to be constantly equal to the input voltage Vin. Accordingly, current i
1
flowing through the p-channel transistor P
1
is given by the following equation (1):
i1=Vr/R=Vin/R  (1)
It will be understood from the above equation (1) that the current i
1
only depends upon the voltage Vin, and does not depend at all upon fluctuations or variations in the power supply voltage, operating temperature, and the manufacturing process. In this example, the device size of the p-channel transistor P
1
is set to be equal to that of the p-channel transistor P
2
. Since these transistors P
1
, P
2
form a current mirror circuit, the current i
1
is equal to current i
2
flowing through the p-channel transistor P
2
.
The voltage Vp and voltage Vn that appear in the V-I converter
1
are then supplied to the ring oscillator
2
. The ring oscillator
2
is constructed as a series connection of a plurality of inverters. The device size of p-channel transistors P
3
-Pn+1 of these inverters is set to be equal to that of the p-channel transistors P
1
, P
2
of the V-I converter
1
, and the device size of n-channel transistors N
2
-Nn is set to be equal to that of the n-channel transistor N
1
of the V-I converter
1
. The p-channel transistors P
3
, P
5
, . . . Pn on the side of the positive power supply form a current mirror circuit with the p-channel transistors P
1
, P
2
of the V-I converter
1
, and the n-channel transistors N
3
, N
5
, . . . Nn on the ground side also form a current mirror circuit with the n-channel transistor n
1
of the V-I converter
1
. Thus, the current flowing through each inverter is equal to the current i
1
.
Generally, the delay time T of each inverter is represented by: T=CV/i, where C represents the gate is capacitance of transistors of the next stage inverter, and V represents the supply voltage. If the ring oscillator is formed of n-stage inverters, therefore, the oscillation frequency f of the voltage-controlled oscillator VCO is approximately calculated according to the following equation (2):
f=n·1/CV=n·Vin/(CV·R)  (2)
It will be understood from the above equation (2) that the oscillation frequency f does not depend on variations in the operating temperature or manufacturing process, but depends on the voltage Vin.
In the actual operation of the voltage-controlled oscillator VCO constructed as described above, however, the current flowing through each inverter needs to be set to be smaller than the current i
1
in view of the relationship with the amplitude of the signal. This point will be described in further detail taking the first-stage inverter as an example.
FIG. 2
shows the configuration of the inverter in the first stage of the ring oscillator
2
.
FIG. 3
shows the waveform of the signal voltage V that is the drain voltage of the p-channel transistor P
4
. As shown in
FIG. 3
, the signal voltage V exceeds the drain voltage of the p-channel transistor P
1
during a period of time T1, and falls below the drain voltage of the n-channel transistor N
1
during a period of time T2. During these periods T1, T2, therefore, the voltage VDS between the drain and source of each of the p-channel transistor P
3
and the n-channel transistor N
3
is reduced to a low value.
FIG. 4
shows a general relationship between the drain-source voltage VDS and the drain current id. In
FIG. 4
in which VDS
1
denotes the voltage between the drain and source of the p-channel transistor P
1
and VDS
3
denotes the voltage between the drain and source of the p-channel transistor P
3
, the drain-source voltage VDS
1
is located in the saturation region and the drain-source voltage VDS
3
is located in the non-saturation region as shown in
FIG. 4
, with the result that the current i
1
becomes larger than the current i
3
. Since the oscillation frequency f is proportional to the current i flowing through each inverter according to the above expression (2), the known voltage-controlled oscillator VCO suffers from a problem that the oscillation frequency f is reduced due to the reduced current i
3
.
To avoid the above problem, a voltage-controlled oscillator as shown in
FIG. 5
is proposed in “A Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3V/5V Operation” IEEE J. Solid-State Circuits vol. 32, No. 4, April 1997 p.582-586.
In the voltage-controlled oscillator VCO of
FIG. 5
, a control signal CS is supplied to each gate of n-channel transistors N
10
, N
20
via a control input terminal CONT. If all of p-channel transistors P
10
-P
90
have the same device size, the voltage Vp
1
between the positive power supply voltage (source) and the gate of the p-channel transistor P
40
is smaller than the voltage Vp
2
between the power supply voltage and the gate of the p-channel transistor P
50
(namely, Vp
1
<Vp
2
). Also, the same current flows through the p-channel transistor P
40
, P
50
having the same device size, and therefore Vp
1
is obtained by subtracting nA from Vp
2
, i.e., Vp
1
=Vp
2
−nA, where nA is the source-drain voltage of the p-channel transistor
40
.
Accordingly, the source-drain voltage nA of the p-channel transistor P
40
on the side of the positive power supply is equal to Vp
2
−Vp
1
, thus eliminating the above problem encountered in the circuit of
FIG. 1
that the drain-source voltage is reduced with the result of restricted or reduced current.
In the voltage-controlled oscillator VCO as shown in
FIG. 5
, however, the voltage Vp
1
and voltage Vp
2
depend on fluctuations or variations in the power supply voltage, operating temperature, and/or the manufacturing process, as well as the input voltage Vin. Thus, the known voltage-controlled oscillator VCO suffers from variations or changes in the relationships of the oscillation frequency f with the input voltage Vin.
SUMMARY OF THE INVENTION
It is therefore an object of the

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